Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-07-06
2002-03-26
Fahmy, Wael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S486000
Reexamination Certificate
active
06362027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure of a semiconductor device such as an insulated gate transistor having a wiring made of an aluminum material and a method of manufacturing the semiconductor device. Also, the present invention relates to an active matrix substrate having a scanning line made of an aluminum material and a method of manufacturing the active matrix substrate.
It should be noted that the semiconductor device of the present invention includes not only elements such as a thin film transistor or a MOS transistor but also an electronic equipment having a semiconductor circuit formed of insulated gate semiconductor elements and an electronic equipment such as a personal computer or a digital camera having an electro-optic display device (representatively, a liquid crystal display device) formed of an active matrix substrate.
2. Description of the Related Art
Attention has been now paid to an active matrix liquid crystal display having a pixel matrix circuit and a drive circuit made up of a thin film transistor (hereinafter referred to as “TFT”) formed on an insulating substrate. There are the liquid crystal display for a projector which is about 0.5 to 2 inches in size and the liquid crystal display for a note-type personal computer which is about 10 to 20 inches in size. Thus the liquid crystal display is used as a small-sized display or a middle-sized display.
The liquid crystal display has been so developed as to increase the display area. However, an increase in the display area causes a pixel matrix circuit which forms an image display section to increase in area, with which source wirings, gate wirings and so on which are arranged in a matrix become long, to thereby increase a wiring resistance. Further, since it is necessary to thin the wirings in response to a request for fining, an increase in the wiring resistance is more actualized. Also, a TFT is connected to the source wirings and the gate wirings for each of pixels, and an increase in the number of pixels leads to a problem that a parasitic capacitance increases. In the liquid crystal display, the gate wirings and the gate electrodes are generally integrated with each other, whereby a delay of gate signals is actualized with an increased area of the panel.
Under the above-mentioned circumstance, the gate wirings are made of a material mainly containing aluminum low in specific resistance. When the gate wirings and the gate electrodes are made of the material mainly containing aluminum, a gate delay time can be shortened, and also the TFT can be operated at a high speed. In general, in the case where the gate wirings are made of the aluminum material, aluminum is coated with an anodic oxide film so as to improve the heat resistance of the wirings.
Also, up to now, an attempt has been made that the thin film transistor is brought in an offset structure or an LDD (light doped drain) structure, to thereby reduce an off-state current. In Japanese Patent Publication No. 2759415, the present applicant teaches a technique by which the thin film transistor of the LDD structure is manufactured. The above-mentioned patent publication discloses a method in which a gate electrode made of aluminum is anodically oxidized to form the LDD structure on a semiconductor layer in a self-aligning manner. This method will be described with reference to
FIGS. 49A
to
49
F.
An under film
11
such as a silicon oxide film is formed on a glass substrate
10
. A semiconductor layer
13
consisting of a polycrystal silicon film is formed on the under film
11
, and a gate insulating film
14
is formed on the semiconductor layer
13
. Then, an aluminum film is formed on the upper surface and patterned by using a resist mask
16
to form a gate electrode
15
made of aluminum (FIG.
49
A).
The gate electrode
15
is anodically oxidized in an electrolyte to form a porous alumina film
17
. An oxalic acid aqueous solution is used for the electrolyte. Because the surface of the gate electrode
15
is covered with the resist mask
16
, the porous alumina film
17
is formed only on side surfaces of the gate electrode
15
. In this specification, the porous alumina film
17
is mentioned as “porous A.O. film
17
” (FIG.
49
B).
After the removal of the resist mask
16
, the gate electrode
15
is again anodically oxidized to form a barrier (non-porous) alumina film
18
. Ethylene glycol aqueous solution containing tartaric acid of several % therein is used for an electrolyte. An aluminum pattern remaining through two anodic oxidation process functions as a gate electrode
15
′. In this specification, the barrier alumina film
18
is mentioned as “barrier A.O. film
18
” (FIG.
49
C).
Then, the gate insulating film
14
is patterned with the A.O. films
17
and
18
as a mask to form a gate insulating film
14
′ (FIG.
49
D).
After the removal of the porous A.O. film
17
, the semiconductor layer
13
is doped with impurities that give an n-type or p-type conductivity through the plasma doping method. The doping process is implemented twice. A first doping process is conducted at a low acceleration so that the gate insulating film
14
′ functions as a mask, and the dose amount is set to be large. A second doping process is conducted at a high acceleration so that the impurities pass through the gate insulating film
14
′, and the dose amount is set to be small in order to form an LDD region. In the semiconductor layer
13
, a channel formation region
20
, a source region
21
, a drain region
22
and lightly-doped impurity regions
23
,
24
are formed in a self-aligning manner. The lightly-doped impurity region
24
on the drain region
22
side constitutes the LDD region. When the gate insulating film
14
′ is allowed to function as a complete mask during the doping process, the regions
23
and
24
can be constituted as an offset region (FIG.
49
E).
Subsequently, an interlayer insulating film
25
that covers the TFT is formed on the upper surface. Then, contact holes are opened in the interlayer insulating film
25
, into which source and drain electrodes
26
and
27
are formed. Finally, a hydrogenation process is conducted to complete the TFT (FIG.
49
F).
The application of an anodic oxidation process enables a TFT of the LDD structure or the offset structure to be formed in the self-aligning manner.
However, in order to conduct the anodic oxidation process, it is necessary to connect all of the electrodes and wirings to be anodically oxidized to a voltage supply wiring for anodic oxidation. For example, in the case where the technique disclosed in the above-mentioned Japanese Patent Publication is applied to the active matrix liquid crystal panel, it is necessary to connect all of the active matrix circuit and the gate electrode/wiring of the thin film transistor that constitutes a driver circuit to the voltage supply line. For achieving this connection, it is necessary to form the voltage supply wiring on the substrate, and a surplus space must be ensured.
Also, the structure is made so that the respective gate electrodes and the wirings are short-circuited by the voltage supply line at the time of anodic oxidation. Because the voltage supply line and the connection portions to the voltage supply line are not required after the anodic oxidation process, they are removed by etching so that the respective gate wirings and electrodes are cut off. To achieve this operation, a circuit arrangement must be designed taking a space in which the voltage supply line is formed and an etching process margin into consideration.
Accordingly, in manufacturing the transistor using the anodic oxidation process, the space in which the voltage supply line is formed and the etching margin are required, which impedes the high integration of the circuit and the reduction of the base area. In addition, since aluminum is exposed from the cut-off faces of the wirings, the heat resistance is deteriorated.
Also, in the TFT shown in
FIGS. 49A
to
49
F, the
Adachi Hiroki
Yamazaki Shunpei
Brewster William M.
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Fahmy Wael
Semiconductor Energy Laboratory Co,. Ltd.
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