Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-06-29
2002-05-28
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S311000, C430S394000, C430S396000, C430S397000
Reexamination Certificate
active
06395456
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the semiconductor devices as well as methods of forming resist patterns and exposure systems used therefor. The invention more particularly relates to semiconductor devices achieving higher integration without deterioration in electrical characteristics thereof and methods of manufacturing the semiconductor devices, as well as methods of forming resist patterns and exposure systems used therefor.
2. Description of the Background Art
Demand for reduced scale and increased integration of semiconductor devices represented by the semiconductor memory device or the like is increasing nowadays. In order to attain such decrease and improvement in scale and integration respectively, the semiconductor has a spacing between interconnection lines that is approximately equal to or smaller than the wavelength of exposure light for the photolithography process in the step of fabricating the interconnection lines. If a through hole is formed in an interlayer insulating film such that the hole is located between the interconnection lines without contacting with the interconnection lines, the through hole should have its diameter smaller than the distance between the interconnection lines. In other words, the through hole having its diameter smaller than the wavelength of the exposure light must be made. For example, if KrF excimer laser (wavelength 248 nm) is employed as the exposure light, a through hole with a diameter of about 200 nm is required. If i-ray (wavelength 365 nm) is employed, a through hole with a diameter of about 300 nm is required.
The through hole is used for electrically connecting an underlying conductive region and an overlying interconnection line. The overlying interconnection line should be formed to overlap the through hole. However. considering the overlay accuracy of a photolithography used for forming the overlying interconnection line, the diameter of the through hole preferably has a size defined by taking it into account at least the width and the margin (tolerance) of pattern position accuracy of the overlying a interconnection line, in order to superimposing the overlying interconnection line surely on the through hole. The through hole then needs the diameter significantly greater than the wavelength of the exposure light.
A semiconductor device as shown in
FIG. 21
has a structure which satisfies the two requirements above, for example.
FIG. 21
is a plan view illustrating the semiconductor device associated with the present invention.
Referring to
FIG. 21
, lower-level interconnection lines
115
a
to
115
e
such as gate electrodes are formed on a semiconductor substrate (not shown). A conductive region (not shown) is formed between lower-level interconnection lines
115
a
to
115
e
at a main surface of the semiconductor substrate. An interlayer insulating film (not shown) is formed on lowerlevel interconnection lines
115
a
to
115
e
. Contact holes
116
a
to
116
f
are formed in the interlayer insulating film in a region between lower-level interconnection lines
115
b
and
115
c
and a region between lower-level interconnection lines
115
d
and
115
e
. Upper-level interconnection lines
117
a
to
117
c
are formed on the interlayer insulating film and in contact holes
116
a
to
116
f
extending in a direction almost. perpendicular to the direction in which lower-level interconnection lines
115
a
to
115
e
extend.
The spacing between lower-level interconnection lines
115
a
to
115
e
is approximately equal to or smaller than the wavelength of exposure light used for generating lower-level interconnection lines
115
a
to
115
e
. Considering this, the shortest, distance across each of contact holes
116
a
to
116
f
(minor axis) should be smaller than the wavelength of the exposure light.
Preferably, the longest distance across contact holes
116
a
to
116
f
each (major axis) is greater than the combined length of the line width of upper-level interconnection lines
117
a
to
117
c
each and a margin of pattern position accuracy &Dgr;M. This arrangement is made for surely making contact between upper-level interconnection lines
117
a
to
117
c
and the conductive region on the semiconductor substrate via contact holes
116
a
to
116
f
even if the positions of upper-level interconnection lines
117
a
to
117
c
change due to varying factors in manufacture such as an overlay error of a mask.
A mask pattern illustrated in
FIG. 22
is used for making such contact holes
116
a
to
116
f
.
FIG. 22
illustrates the mask pattern used for generating contact holes
116
a
to
116
f
shown in FIG.
21
.
Referring to
FIG. 22
, a mask pattern
110
is generated at a lightblocking film
109
. Mask pattern
110
has a width Wm
4
and a height Hm
4
. If mask pattern
110
is for a reduction exposure step using a stepper, the size of mask pattern
110
is about five times larger than that of a resist pattern formed at a resist film on the semiconductor substrate. For an exposure system such as a scan type having a different reduction ratio of 4 to 1, the size of the mask pattern is about four times larger than, or inverse of the reduction ratio times larger than that of the resist pattern.
FIG. 23
illustrates a resist pattern to be formed by using the mask pattern shown in FIG.
22
. Referring to
FIG. 23
, a resist pattern
112
a
having a width W
3
and a height H
3
is formed at a resist film
11
.
If resist pattern
112
a
to be formed has the width W
3
which is sufficiently greater than the wavelength of the exposure light, the ratio between the width W
3
and height H
3
of resist pattern
112
a
is almost close to the ratio between the width Wm
4
and the height Hm
4
of mask pattern
110
shown in FIG.
22
. Accordingly, resist pattern
112
a
similar to an ellipse as shown in
FIG. 23
is obtained. Referring again to
FIG. 23
, if the distance HS between resist pattern
112
a
to be formed and another resist pattern adjacent thereto is sufficiently greater than the wavelength of the exposure light, the shape, size, position and the like of resist pattern
112
a
can easily be corrected.
However, if the width W
3
of resist pattern
112
a
to be formed is smaller than the wavelength of the exposure light, the ratio of a height H
4
to a width W
4
of a resist pattern
112
b
is smaller than the ratio of the height Hm
4
to the width Wm
4
of mask pattern
110
of the mask used for the exposure step as shown in FIG.
24
. As a result, the two-dimensional shape of thus obtained resist pattern
112
b
becomes similar to a circle as shown in FIG.
24
.
FIG. 24
illustrates the resist pattern generated by using the mask pattern shown in
FIG. 22
when the shortest distance across the resist pattern is smaller than the wavelength of the exposure light.
In such a case, resist pattern
112
a
as shown in
FIG. 23
is not obtained. and accordingly, it is difficult to form contact holes
116
a
to
116
f
each having the sufficient longest distance across the contact hole. When upper-level interconnection lines
117
a
to
117
c
are formed, if the longest distance across contact holes
116
a
to
116
f
each is not enough, the positions of upper-level interconnection lines
117
a
to
117
c
and of contact holes
116
a
to
116
f
could not match.
A problem consequently arises is that electrical connection of the conductive region on the semiconductor substrate with upper-level interconnection lines
117
a
to
117
c
is impossible. This problem causes deterioration of electrical characteristics of the semiconductor device. For example, a circuit in the semiconductor device does not operate correctly. A problem thus generated is reduction in the yield of the semiconductor device.
In order to avoid decrease in the height H
4
of resist pattern
112
b
as shown in
FIG. 24
, a mask pattern shown in
FIG. 25
can be used.
FIG. 25
illustrates another mask pattern associated with the present invention.
Tamada Naohisa
Yamada Yoshiaki
Barreca Nicole
Huff Mark F.
Mitsubishi Denki & Kabushiki Kaisha
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