Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2001-03-08
2004-06-29
Wong, Don (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S686000, C361S702000, C315S307000
Reexamination Certificate
active
06756661
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, a semiconductor module loaded with the semiconductor device, and a manufacturing technique of the semiconductor module, and particularly relates to a tape carrier type semiconductor device (TCP: Tape Carrier Package) for mounting plural chips to one tape, and an effective technique applied to a semiconductor module loaded with plural TCPs.
BACKGROUND OF THE INVENTION
For example, when a memory TCP such as a DRAM is made as a conventional manufacturing technique of the tape carrier package, there is a one-chip built-in TCP package in which a series of insulating tapes forming lead wiring therein is used, and an individual memory chip is sequentially mounted to these insulating tapes, and the memory chip and the lead wiring are finally set to a pair.
In manufacture of this memory TCP, for example, in a selecting process, a material processed in a tape shape so far is conveyed in a state in which this material is cut into an individual piece. For example, it is indispensable in this individual tape piece described in Japanese Patent Laid-Open No. 37141/1994 that a pad for a test probe is arranged around an outer lead. An outer shape size of the individual tape piece is four times or more in area in comparison with a TSOP (Thin Small Outline Package), etc. Accordingly, a socket for burn-in and a test is also four times or more in area in comparison with the TSOP. Further, when the test is terminated, the individual tape piece is cut in an outer lead portion in a final process, and the outer lead is formed in a gull-wing shape, and is stored to a tray.
Further, for example, when this memory TCP is produced as a memory module, the memory TCP is again picked up one by one from the tray, and plural memory TCPs are mounted onto a substrate and are completed as a memory module of a predetermined capacity in a module mounting process.
SUMMARY OF THE INVENTION
With respect to the technique of the memory TCP mentioned above and the memory module loaded with this memory TCP, the following contents have become clear as a result of consideration of the prevent inventors. For example, in manufacture of the memory TCP, the individual tape piece for burn-in and a test is large in size so that a socket size mountable in comparison with the TSOP is increased. Therefore, the number of sockets attached to a board for burn-in and a test is greatly reduced. As a result, a processing number is reduced, in other words, cost is increased.
Further, the material is conveyed in a tape state until a seal process in a TAB (Tape Automated Bonding) process itself. However, after the selecting process, the material is individually cut, and is again mounted to the memory module one by one in the memory module mounting process. This is disadvantageous in view of mounting cost and mounting area. Accordingly, it is considered that an efficient process at low cost is realized if the tape is supplied to the memory module process as it is, and the tape can be simultaneously cut and mounted to the substrate.
As an example of the memory module, for example, there is a memory module described in Japanese Patent Laid-Open No. 350961/1992. In this memory module, lead wiring of the tape is set to multiple layers, and plural chips mounted through an insulating film are electrically connected to each other. In this technique, the lead wiring of the tape and a chip are connected to each other by wire bonding, and it is necessary to draw lead wiring for a common signal common to chips around one side of the module so that a wiring layer is required every common signal. Accordingly, the number of layers in a tape structure is extremely large. Therefore, it is considered that it is difficult to design the tape and it is disadvantageous in cost.
Therefore, an object of the invention is to provide a semiconductor device able to reduce tape cost and burn-in and test cost by simplifying a tape design and increasing a simultaneous processing number in burn-in and test using an assembly process of a TCP, and further provide a semiconductor module able to reduce substrate cost and module mounting cost by mounting plural semiconductor devices and simplifying a substrate design and efficiently performing module mounting.
The above and other objects and novel features of the invention will become apparent from the description and the accompanying drawings of the present specification.
Summaries of typical inventions among the inventions disclosed in the present application will be explained briefly as follows.
Namely, a first semiconductor device in the invention as the structure of a basic multi-chip TCP is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals on the two sides are electrically connected to each other by common signal wiring.
A second semiconductor device in the invention as the structure of a multi-chip TCP able to be divided into two portions is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on the one set of two opposed sides are arranged with left-right mirror symmetry. Further, two mirror symmetry tape carrier type semiconductor devices are formed by cutting the tape at its center.
Further, a third semiconductor device in the invention as the structure of a multi-chip TCP of a lead type is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to the common signal terminals and the independent signal terminal and is projected from the tape, and the common signal terminals on the two sides are electrically connected to each other by common signal wiring. Further, plural support leads electrically unconnected to the mounted chip are arranged on another side opposed to the lead of the independent signal terminal.
Further, a fourth semiconductor device in the invention as the structure of a multi-chip TCP able to be laminated is a tape carrier type semiconductor device for mounting plural chips to one tape in which a semiconductor device having common signal terminals arranged on one set of two opposed sides, a first independent signal terminal arranged on another side, and a second independent signal terminal electrically unconnected to the chips mounted to the tape is laminated, and the first independent signal terminal at an upper stage and the second independent signal terminal at a lower stage are connected to each other, and the second independent signal terminal at the upper stage and the first independent signal terminal at the lower stage are connected to each other. Further, the laminated semiconductor device is laminated by a tape-on-tape structure, a lead-on-tape structure or a lead-on-lead structure.
In the structure of each of the first, second, third and fourth semiconductor devices, pads of the chip are set such that a pad connected to the common signal wiring is arranged far from the independent signal terminal, and a pad connected to independent signal wiring is arranged near the independent signal terminal. Further, the common signal wiring and the independent signal wiring formed on the tape are located on the same face, and do not cross each other.
The tape is a one-layer tape or a two-layer tape. A ground electric potential plane pattern and a power electric potential plane pattern are mainly formed on a face opposed to a forming face of the common signal wiring and the independent signal wiring in the two-layer tape. Further, an insulating material is interposed between a main face of the chip and signal wiring of the
Nagaoka Kouji
Sato Tomohiko
Sugano Toshio
Tsukui Seiichiro
Tsuneda Kensuke
Mattingly Stanger & Malur, P.C.
Vu Jimmy T.
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