Semiconductor device, a method of manufacturing a...

Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed

Reexamination Certificate

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C438S018000, C438S014000, C438S106000, C257SE21531

Reexamination Certificate

active

07816154

ABSTRACT:
A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure
o-failure determination in this performance test is outputted to the tester.

REFERENCES:
patent: 6335565 (2002-01-01), Miyamoto et al.
patent: 6979905 (2005-12-01), Nishida et al.
patent: 2005/0146008 (2005-07-01), Miyamoto et al.
patent: 2007/0096287 (2007-05-01), Araki et al.
patent: 2004-235352 (2004-08-01), None
patent: 2006-38678 (2006-02-01), None
patent: 2007-123454 (2007-05-01), None

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