Semiconductor device

Details Semiconductor device Semiconductor device

2000-09-25

2002-01-22

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S227000

Reexamination Certificate

active

06341087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device suitable for an SOI-type semiconductor device, and more particularly to an improvement to suppress a leak current during standby and a circuit delay during operation.
2. Description of the Background Art
In the present specification, the term “MOS transistor (MOSFET)” broadly includes an insulated gate transistor whose gate electrode is made of a conductive material other than metal as well as made of metal in accordance with the conventional practice in this field. Further, an insulated gate semiconductor element comprising another electrode interposed between a control electrode and a channel region such as a memory element of flash EEPROM is also referred to as a MOS transistor.
For achieving a system LSI, it is known that it is more advantageous in degree of integration, operating speed and power consumption to form a CMOS transistor (complementary MOS transistor: CMOSFET) which is a constituent element of an LSI in a main surface of an SOI (Silicon On Insulator) substrate than in a main surface of a bulk-type semiconductor substrate.
FIG. 20
is a cross section schematically showing a structure of an SOI substrate. In an SOI substrate
100
, a buried oxide layer (BOX layer)
114
made of a silicon oxide is formed on a supporting substrate
113
which is a semiconductor substrate mainly made of a silicon and an SOI layer
115
made of a crystalline silicon is formed further thereon.
The BOX layer
114
has a thickness of about 0.01 &mgr;m to 0.4 &mgr;m and the SOI layer
115
has a thickness of about 0.1 &mgr;m to 1 &mgr;m. MOS transistors are formed in a main surface of the SOI layer
115
. The MOS transistors are isolated from one another by LOCOS or STI (Shallow Trench Isolation). A channel region in an active region of the MOS transistor is also referred to as a body region.
The semiconductor device having an SOI structure constituted of the supporting substrate
113
, the BOX layer
114
and the SOI layer
115
, in which the active region is surrounded by the BOX layer
114
and an isolation insulating film
150
(hereinafter, referred to as “full isolation” or “Full STI: Full Shallow Trench Isolation” and abbreviated to “FTI”) whose bottom surface reaches the BOX layer
114
, has an advantage that no latch up occurs even if the CMOS transistor is formed in the SOI layer
115
. Further, since source/drain regions of the MOS transistor are in contact with the BOX layer
114
, obtained is an advantage that junction capacitance becomes smaller, high-speed operation is available, a leak current during standby becomes smaller and power consumption is reduced as compared with a semiconductor device in which the MOS transistors are formed directly in the main surface of the semiconductor substrate.
When the SOI layer
115
which is a semiconductor layer formed on the BOX layer
114
has a thickness not less than e.g., 0.15 &mgr;m, however, carriers (positive hole in an NMOS transistor and electrons in a PMOS transistor) generated by impact ionization phenomenon are accumulated immediately below the channel region. This raises problems that kink appears in the Ids-Vds characteristic of a transistor and that an operating breakdown voltage is deteriorated. Further, since there are various problems caused by a floating-substrate effect such as frequency dependency appearing in the delay time due to an unstable potential of the channel region, the potential of the channel region is normally fixed. The semiconductor device in which the potential of the channel region is fixed as above is disclosed in Japanese Patent Application Laid Open No. 58-124243 (1983).
Recently has been made an attempt that an isolation insulating film
116
(hereinafter, “partial isolation” or “Partial STI: Partial Shallow Trench Isolation” and abbreviated to “PTI”) whose bottom surface does not reach the BOX layer
114
is used for isolation so as to collectively fix the potentials of the channel regions of a plurality of transistors of the same conductivity type, instead of individually fixing the potentials of the channel regions of MOS transistors, thereby promoting miniaturization. The semiconductor device having this structure is disclosed in IEEE international SOI Conference, October (1997) and the like.
FIG. 21
is a plan view showing a semiconductor device in the background art. In the semiconductor device, an NMOS region and a PMOS region are formed in the SOI layer, and a plurality of NMOS transistors are formed in the NMOS region and a plurality of PMOS transistors are formed in the PMOS region. An active region
102
of each MOS transistor is formed and a pair of source/drain regions
103
and
104
are formed with a channel region interposed therebetween in the active region
102
. One of the source/drain regions
103
and
104
is a source region and the other is a drain region, both of which serve as a source of carriers (electrons or positive holes) or have a function of draining the carriers out, and each of them is referred to as “a source/drain region” in the present specification.
A body contact region
112
is formed in each of the NMOS region and the PMOS region. The body contact region
112
and the active region
102
of each MOS transistor are isolated from each other by a PTI
101
serving as an isolation region. The body contact region
112
is provided to fix the potential of the channel regions (body regions) of a plurality of MOS transistors of the same conductivity type.
Source/drain lines
105
and
107
are connected to the source/drain regions
103
and
104
, respectively. Further, a gate electrode (gate line)
106
is provided above the channel region. The gate electrode
106
is connected to a metal wire
110
through a gate electrode contact
109
. A metal wire
111
is connected to the contact region
112
. An isolation width
108
refers to the width of the PTI
116
which isolates the NMOS region and the PMOS region.
FIG. 22
is a cross section taken along the line A—A off
FIG. 21. A
pair of source/drain regions
103
and
104
are selectively formed with an N-type channel region
122
p
or a P-type channel region
122
n
interposed therebetween in each of the active regions
102
formed in the SOI layer
115
. A high-concentration source/drain region
124
and a low-concentration source/drain region
123
are formed in each of the source/drain regions
103
and
104
. The PTI
116
isolating two adjacent active regions
102
does not reach the BOX layer
114
and a P-type channel stopper
125
and an N-type channel stopper
126
are formed immediately below the PTI
116
.
A gate insulating film
117
is formed on the channel regions
122
p
and
122
n
and the gate electrode
106
having a double-layered structure consisting of a doped polysilicon layer
118
and a metal layer
119
is formed on the gate insulating film
117
. Specifically, the gate electrode
106
is opposed to the channel regions
122
p
and
122
n
with the gate insulating film
117
interposed therebetween. The gate electrode
106
is covered with an insulating film
120
and a sidewall
121
is formed on a side surface of the gate electrode
106
with the insulating film
120
interposed therebetween. The source/drain lines
105
and
107
are connected to the source/drain regions
103
and
104
through contact plugs
131
and
129
penetrating interlayer insulating films
127
and
128
.
The parasitic capacitance of the source/drain region
103
or
104
of the MOS transistor is generated by junction between the same and the channel region
122
p
or
122
n
and that between the same and the channel stopper
125
or
126
. To improve the operating speed of the MOS transistor, it is desirable that the parasitic capacitance should be small.
The leak current of the MOS transistor during standby is caused by a generated current flowing in a depletion layer created by application of reverse bias to a junction formed between the source/drain regions
103
and
104
and the channel reg

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