Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-04-23
2002-05-21
Chaudhari, Chandra (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S211000, C257S212000, C257S758000
Reexamination Certificate
active
06392252
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to a semiconductor device equipped with conformation difference detection circuits for detecting a layering difference of semiconductor integrated circuits.
2. Description of the Prior Art
In general, in a semiconductor device comprising semiconductor integrated circuits, the conformation difference of the semiconductor integrated circuits is always inspected for product inspection of the semiconductor device.
At the time of conformation difference inspection, for example, a vernier pattern previously formed on a substrate of a semiconductor device is used.
At the time of conformation difference inspection by the vernier pattern, an operator inspects the conformation difference using an optical microscope or the like.
Further, Japanese Patent Laid-Open No. 5-3237 discloses a method using detection patterns composed of a lower layer pattern and an upper layer pattern mutually crossing each other and both formed in a void region of a semiconductor device as a technique of inspecting the conformation difference of respective wiring layers. This technique carries out conformation difference inspection of a semiconductor device by measuring the electric resistance at a prescribed point of the lower layer pattern, a detection pattern and calculating the conformation difference based on the measured value.
Further, one example of general detection patterns used conventionally is illustrated in FIG.
15
.
In the conventional example illustrate in
FIG. 15
, the detection pattern is provided with conformation margin widths D
51
, D
54
respectively in the X-direction and Y-direction surrounding the contact faces of a plurality of through holes
53
in the respective upper and lower layer wirings
51
,
54
sides of the contacting faces of the through holes
53
and the respective upper and lower layer wirings
51
,
54
. In this case, the foregoing conformation margin width D
51
shows the conformation margin width in the foregoing lower layer wiring
31
side and the foregoing conformation margin width D
54
shows the conformation margin width in the foregoing upper layer wiring
54
side, respectively. Further, the foregoing respective conformation margin widths D
51
, D
54
show the same widths, respectively, in the X-direction and the Y-direction. Incidentally, in
FIG. 15
, the reference character X denotes the X-direction; the reference character Y denotes the Y-direction; the reference numeral
50
denotes a circuit substrate; and the reference numeral
52
denotes an insulating layer.
In this case, for example, if conformation difference takes place in lower layer wirings
51
and through holes
53
and the electric resistance of each through hole
53
increases by b(delta), the electric resistance increase in the entire detection pattern is the product of &dgr;×N wherein the reference character N denotes the total number of the through holes. Based on the electric resistance increase &dgr;×N, whether the conformation difference is within an allowable range or not is determined. In the case, the reference character N denotes a natural number.
In such a manner, since the increase of the electric resistance of each through hole
53
is generally slight, about several ohm, the abnormality of through holes is detected by measuring the electric resistance of the entire detection pattern.
BRIEF SUMMARY OF THE INVENTION
Object of the Invention
However, although the conventional example using the above described vernier pattern is capable of detecting the conformation difference, there occur problems that, for example, disconnection or the like of the lower layer wirings, caused by a photolithographic technique or an etching technique relevant to semiconductor device fabrication cannot be detected and that the inspection precision of the fine technique is limited owing to the optical inspection by an optical microscope.
Further, in the technique disclosed in Japanese Patent Laid-Open No. 5-3237 and employing the detection pattern, although the technique can detect the disconnection of the lower layer wirings, there occurs a problem that the formation abnormality of through holes caused by photolithographic technique or the like cannot precisely be detected since the pattern cannot have the structure to measure the electric resistance in the inside of a through hole in the detection pattern.
Moreover, in the conventional example using the detection pattern illustrated in
FIG. 15
, although the conformation difference of a semiconductor device can be inspected, the conformation margin widths D
51
, D
54
in the detection pattern are set to be mutually equal in the X-direction and the Y-direction. For that, if there occurs conformation difference, gaps are formed in the contact faces of the through holes
53
owing to the excess of the conformation difference widths D
51
, D
54
independently of the X-direction and the Y-direction to result in increase of the electric resistance in the entire detection pattern. Consequently, a problem takes place that the direction of the conformation difference cannot be detected.
The present invention is to solve such problems of a conventional example and more particularly to provide a semiconductor device in which it is made possible to detect the direction of conformation difference of respective wiring layers of semiconductor integrated circuits and to increase the detection sensitivity.
Summary of the Invention
In order to attain the above described purposes, the respective inventions as set forth in claim
1
to claim
5
propose a semiconductor device having a common basic structure comprising: one or more of semiconductor integrated circuits formed on a semiconductor substrate; and conformation difference detection circuits formed on the same semiconductor substrate; to detect the layering difference of the semiconductor integrated circuits,
wherein the conformation difference detection circuits are so composed of a plurality of lower layer wirings formed on the semiconductor substrate, a plurality of upper layer wirings layered on the lower layer wirings through insulating layers, through holes successively and respectively contacting the respective upper layer wirings and the lower layer wirings in prescribed directions, and electrode terminal faces set in both end parts of the circuits composed of the lower layer wirings and the upper layer wirings contacted through the through holes as to keep conformation margins with prescribed widths surrounding the contact faces of the through holes in the respective wiring sides in the contacting faces of the through holes and the respective wirings; and
the widths of the conformation margins are so adjusted as to be narrower in one prescribed direction than the direction other than the prescribed direction.
For that, in the present invention as set forth in claim
1
to claim
5
, gaps are made easy to be formed in the through hole contact faces in the one direction and as compared with a case where conformation difference in a prescribed extent is caused in the other direction, in the case where conformation difference in a prescribed extent is caused in the one direction, it is easy to exceed the conformation margin width. Consequently, even if a slight conformation difference takes place in the one direction, the conformation margin width is exceeded and, therefore, gaps are formed in the through hole contact faces in the one direction and the electric resistance of a conformation difference detection circuit increases and exceeds an allowable range. As a result, the detection sensitivity of conformation difference caused in a specified direction can be improved.
In this case, the prescribed circuits composed of the lower layer wirings and the upper layer wirings contacted through a plurality of through holes may be formed to be contacted circuits by continuously extending the circuits as a whole in one prescribed direction in a prescribed length.
Doing so, t
Chaudhari Chandra
Hayes & Soloway P.C.
Huynh Yennhu B.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2865576