Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – Field relief electrode
Reexamination Certificate
2000-08-09
2002-09-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
Field relief electrode
C257S104000, C257S489000
Reexamination Certificate
active
06452245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to formation of a wire in the neighborhood of a contact.
2. Description of the Related Art
As a technique for forming a high-withstand contact, which is suitable for use in a semiconductor device, there is known one wherein a P-type high-concentration impurity diffused region is formed in an N-type semiconductor substrate, an aperture or opening is defined in an oxide film on the substrate at a portion corresponding to the P-type high-concentration impurity diffused region, and a wiring layer is formed over the opening and the oxide film, thereby forming a drawing or lead wire.
In such a structure, a depletion layer is formed over the surface of the semiconductor substrate located below the wire. An N-type high-concentration impurity diffused region might be formed at a portion spaced by a predetermined distance from the P-type high-concentration impurity diffused region so as to avoid an excessive expansion of the depletion layer. There might be cases where even in this structure, a desired element characteristic was not obtained due to a problem such as concentration of an electric field with an increase in voltage to be handled.
Thus, in the preceding application (Japanese Patent Application No. Hei 10-17848) made by the inventors of the present application, each of conductive material layers being placed under the same potential as a substrate potential was formed over an oxide film placed over a semiconductor substrate, an interlayer dielectric was formed over the conductive material layers, and a wiring layer drawn from an opening was formed over the interlayer dielectric, thereby controlling a region for forming a depletion layer.
However, it has been confirmed by the inventors that in the conventional structure of the drawing or lead wire placed in the vicinity of the contact, a sufficient withstand voltage cannot be obtained depending on how to cross the wiring layer and the conductive material layers.
SUMMARY OF THE INVENTION
In order to solve the foregoing problems, there is provided a semiconductor device according to the present invention, comprising a second conduction type impurity diffused region formed over the surface of a first conduction type semiconductor substrate, a first conduction type impurity diffused region formed over the surface of the semiconductor substrate in a concentration higher than an impurity concentration of the semiconductor substrate with a predetermined interval left from the second conduction type impurity diffused region, a first insulating film formed over the semiconductor substrate, conductive material layers each formed over the semiconductor substrate placed between the second conduction type impurity diffused region and the first conduction type impurity diffused region or over the first insulating film above said first conduction type impurity diffused region, each conductive material layer having a predetermined radius of curvature in the direction of a plane as viewed from an upper surface of the substrate, a second insulating film formed over the conductive material layers and the first insulating film, an opening defined in the first and second insulating films above the second conduction type impurity diffused region, and a wiring layer formed over the opening and the second insulating film, and wherein the direction in which the wiring layer extends in the plane direction as viewed from the upper surface of the substrate, is defined as a first direction, the direction orthogonal to the first direction on the plane is defined as a second direction, a radius of curvature of the conductive material layer closest to the opening is defined as R, a point where the conductive material layer and an end of the wiring layer intersect on the plane, is defined as X, a point where a straight line extending along the second direction from the point X intersects a straight line extending along the first direction through the center of the radius R of curvature of the conductive material layer, is defined as Y, and the distance between the points X and Y with respect to the second direction is defined as A, whereby the relations in COS
−1
(A/R)>46 are established.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
REFERENCES:
patent: 5434445 (1995-07-01), Ravanelli et al.
patent: 59-154056 (1984-09-01), None
patent: 11-204632 (1999-07-01), None
Ishikiriyama Mamoru
Sasaki Katsuhito
Volentine & Francos, PLLC
Vu Hung Kim
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