Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-11
2002-07-16
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06420743
ABSTRACT:
TECHNICAL ART
The present invention relates to a semiconductor device and, more particularly, to improvements in variations in characteristics and characteristic deterioration in a ferroelectric memory device.
BACKGROUND ART
As conventional semiconductor devices, there have been developed various circuits from relatively small-sized integrated circuits mounting, for example, an amplifier circuit, an oscillating circuit, a power supply circuit and the like, to relatively large-sized integrated circuits, such as a microprocessor and a memory device. Especially in recent years, as a kind of non-volatile memory device, a ferroelectric memory device with ferroelectric capacitors as capacitors constituting memory cells has been contrived.
The ferroelectric capacitor consists of a pair of electrodes opposite to each other, and a dielectric layer comprising a ferroelectric material and sandwiched between both electrodes, and has the hysteresis characteristic as a relationship between a voltage applied between the both electrodes and polarizability of the ferroelectric material. That is, the ferroelectric capacitor has a construction in which even when the electric field (applied voltage) is zero, a remaining polarization of a polarity in accordance with the hysteresis of voltage application remains in the ferroelectric layer, and in the ferroelectric memory device non-volatility of the storage data is realized by representing storage data by the remaining polarization of the ferroelectric capacitor.
In a non-volatile memory device using such ferroelectric capacitors, it is an important objective to reduce variations in the hysteresis characteristics of the ferroelectric capacitors and reduce changes in the hysteresis characteristic accompanying the use.
More specifically,
FIGS. 14
to
16
are diagrams for explaining a conventional ferroelectric memory device,
FIG. 14
is a plan view illustrating a memory cell array in the ferroelectric memory device,
FIG. 15
is a cross-sectional view along a line XV—XV portion in
FIG. 14
, and
FIG. 16
is a plan view illustrating a position relation between upper electrodes and a lower electrode of ferroelectric capacitors.
In the figures, reference numeral
200
designates a memory cell array constituting a ferroelectric memory device, a plurality of transistor regions
220
a
are arranged on a silicon substrate
201
in a first direction D
1
, and an insulating film
202
for element isolation is formed on a portion of the silicon substrate
201
, except the transistor regions
220
a.
On both sides of the transistor regions
220
a
in a line along the first direction D
1
, lower electrodes (first electrodes)
211
are formed as cell plate electrodes on the insulating film
202
for element isolation via first interlayer insulating films
203
. The lower electrode
211
comprises a metallic material, such as titanium and platinum, and has a stripe-shaped plan configuration extending along the first direction D
1
. On surfaces of the lower electrodes
211
, ferroelectric layers
213
are formed.
On the ferroelectric layers
213
on the surfaces of the lower electrodes
211
, upper electrodes (second electrodes)
212
comprising a metallic material, such as titanium and platinum, are formed corresponding to the respective transistor regions
220
a
. That is, on the ferroelectric layers
213
, the plurality of upper electrodes
212
are arranged along the first direction D
1
. A plan shape of each upper electrode
212
is a rectangular shape having the first direction D
1
as its longitudinal direction, and as is known from
FIG. 14
, the area of each upper electrode
212
is smaller than that of the lower electrode
211
. Here, ferroelectric capacitors
210
are constituted by the lower electrode
211
, the upper electrodes
212
, and the ferroelectric layer
213
located between these electrodes, and the surfaces of the ferroelectric layers
213
and the surfaces of the upper electrodes
211
are covered with second interlayer insulating films
204
.
In this case, the upper electrode
212
is disposed in a center portion of the lower electrode
211
, and the distance O
11
(hereinafter referred to as non-overlap width) between a side
211
a
1
of the lower electrode
211
and a side
211
a
1
of the upper electrode
211
opposite thereto is made equal to the distance O
12
(hereinafter referred to as non-overlap width) between the other side
211
a
2
of the lower electrode
211
and a side
211
a
2
of the upper electrode
211
opposite thereto.
Between the pair of lower electrodes
211
that sandwich the transistor regions
220
a
opposing to each other, a pair of word lines (second wirings)
223
a
and
223
b comprising polysilicon are disposed so as to straddle over the plurality of transistor regions
220
a
arranged in a line. A source diffusion region
222
and drain diffusion regions
221
of a memory transistor
220
constituting a memory cell are formed on both sides of the word lines
223
a
and
223
b
in each transistor region
220
a
. Portions of the word lines
223
a
and
223
b
located above each transistor region
220
a
constitute gate electrodes of the memory transistor
220
, and are located on the substrate surface via gate insulating films
202
a
. The surfaces of the diffusion regions
221
and
222
and the word lines
223
a
and
223
b
are covered with the first and second interlayer insulating films
203
and
204
. In
FIG. 14
, these interlayer insulating films are not shown.
The source diffusion region
222
located between the pair of word lines
223
a
and
223
b
in each transistor region
220
a
is connected to a bit line
233
b
extending along a second direction D
2
perpendicular to the first direction D
1
, through a contact hole
205
b
formed in the first and second interlayer insulating films
203
and
204
. The drain diffusion regions
221
located outside the opposite word lines
223
a
and
223
b
in each transistor region
220
a
are electrically connected to the upper electrodes
212
by connecting wirings
233
a
. That is, one end of the connecting wiring
233
a
is connected to the upper electrode
212
through a contact hole
204
a
formed in the second interlayer insulating film
204
, and the other end of the connecting wiring
233
a
is connected to the drain diffusion region
221
through a contact hole
205
a
formed in the first and second interlayer insulating films
203
and
204
.
The lower electrodes
211
and the ferroelectric layers
213
are formed by successively forming films of a metallic material, such as titanium and platinum, and a ferroelectric material on the interlayer insulating film
203
and patterning these films, and the upper electrodes
212
are formed by forming a film of a metallic material, such as titanium and platinum, on the ferroelectric layer
213
and patterning the film. The bit lines
233
b
and the connecting wirings
233
a
are formed by patterning a metallic film, such as aluminum, formed on the interlayer insulating film
204
. The word lines
223
a
and
223
b
are formed by patterning a polysilicon film that is formed on the gate insulating films
202
a
and the insulating film
202
for element isolation.
The first interlayer insulating film
203
comprises an insulating material, such as NSG (oxide silicon based) and BPSG (boron, phosphine doped oxide silicon), and the second interlayer insulating film
204
comprises, for example, PSG (phosphine doped oxide silicon).
As the ferroelectric material composing the ferroelectric layer
213
of the ferroelectric capacitors, KNO
3
, PbLa
2
O
3
-ZrO
2
-TiO
2
, PbTiO
3
-PbZrO
3
or the like has been known. In addition, PCT International Publication WO 93/12542 discloses a ferroelectric material that has extremely low fatigueness as compared with PbTiO
3
-PbZrO
3
, being suitable for a ferroelectric memory device.
The operation will be described briefly.
In the ferroelectric memory device with the construction as described above, when, for example, the word line
223
a
is selected and subsequently, one
Hirano Hiroshige
Takeo Masato
Burr & Brown
Loke Steven
Matsushita Electronics Corp.
Nguyen Cuong Quang
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