Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-06-29
2002-05-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S774000
Reexamination Certificate
active
06384485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device utilizing a multi-layer substrate having a power-supply plane, a ground plane, and signal lines disposed in layers.
2. Description of the Background Art
One example of a conventional semiconductor device is shown in
FIGS. 9 and 10
. This semiconductor device is the so-called FCBGA (Flip Chip Ball Grid Array) substrate. In the following, in order to discriminate this FCBGA substrate from a simple substrate portion, the overall package will be referred to as a “FCBGA substrate module”
100
. The semiconductor device is provided with a BGA (Ball Grid Array) substrate
101
and a semiconductor chip
102
connected by flip-chip bonding to BGA substrate
101
via a solder bump
105
serving as an electrode. BGA substrate
101
is a substrate having a multi-layer structure, and on its back surface a solder ball
106
serving as an external connection electrode is arranged for providing an electrical connection with the outside. An encapsulation material
104
fills between BGA substrate
101
and semiconductor chip
102
in order to improve the reliability of the bonding between the two. In addition, above semiconductor chip
102
, a heat spreader
107
is provided with a resin for heat radiation
108
provided therebetween in order to radiate the heat generated from semiconductor chip
102
to the outside. Resin for heat radiation
108
is provided to help the heat radiation from semiconductor chip
102
to heat spreader
107
. A ring
103
is provided surrounding semiconductor chip
102
in order to maintain a prescribed distance between BGA substrate
101
and heat spreader
107
as well as to provide strength to the overall package.
Moreover, to facilitate the understanding of the internal structure,
FIG. 9
shows heat spreader
107
partially cut away. In addition,
FIGS. 9 and 10
are schematic diagrams whose dimensional ratio is exaggerated and which represent fewer numbers of solder bumps
105
and solder balls
106
than are actually present for greater clarity.
FIG. 11
shows, in enlargement and in further detail, the portion corresponding to the left half of
FIG. 10. A
multi-layered BGA substrate
101
is provided with plane layers
10
and
11
having copper planes
13
and
14
formed by plating on either surface of a core layer
8
formed of a BT (Bismaleimd Triazine) resin, for instance, and is formed by a plurality of layers further provided evenly on both outer surfaces of plane layers
10
and
11
. For convenience, the portion of the plurality of layers above core layer
8
will be referred to as an “upper multi-layer portion,” and the portion below core layer
8
will be referred to as a “lower multi-layer portion.” Within the upper multi-layer portion and the lower multi-layer portion, a signal layer
9
, a power-supply plane layer
10
, and a ground plane layer
11
are inserted in a certain order at substantially even intervals. Each of these inserted layers will be referred to as a “component layer.”
Signal layer
9
is provided mainly for the laying of a signal line
12
in the lateral direction, i.e., the so-called “routing.” Power-supply plane layer
10
is provided mainly for the disposition of a power-supply plane which is a conductor plane for supplying power. Ground plane layer
11
is provided mainly for the disposition of a ground plane which is a grounded conductor plane.
Solder bumps
105
serving as electrodes for semiconductor chip
102
can be categorized into two kinds based on the function: a signal-related solder bump
105
a
and a non-signal-related solder bump
105
b
. Signal-related solder bump
105
a
is for communicating a signal and is electrically connected to one of solder balls
106
. Non-signal-related solder bump
105
b
is normally connected to a power-supply plane
13
or a ground plane
14
.
Signal-related solder bump
105
a
must be connected to a solder ball
106
via the upper multi-layer portion, core layer
8
, and the lower multi-layer portion. The connection in the lateral direction in the same layer is provided by routing of signal line
12
, and the connection to a lower layer is provided through a via hole
17
.
When disposing signal lines
12
in one signal layer
9
, as a rule, the so-called strip structure is employed, where signal layer
9
is sandwiched between plane layers in order to prevent the crosstalk noise between an upper and a lower signal lines
12
. Therefore, as shown in
FIG. 11
, when the uppermost component layer is a first signal layer
9
, ground plane layer
11
which is one kind of plane layer is disposed as the component layer under the uppermost component layer. Under ground plane layer
11
a second signal layer
9
is disposed, and thereunder, power-supply plane layer
10
which is one kind of plane layer is disposed.
In this example of the FCBGA substrate module, solder bumps
105
are disposed substantially in a belt-like shape only in the peripheral portion on the bottom surface of semiconductor chip
102
. The number of rows of signal-related solder bumps
105
a
counted in the width direction of the band is six to seven. Signal-related solder bump lands
16
a
serving as chip electrode lands for these electrodes are disposed in a similar manner. Signal-related solder bump lands
16
a
must be connected to the respective solder balls
106
via certain paths. The manner of connection will be described in relation to
FIGS. 12
to
14
.
FIGS. 12 and 13
represent the signal flow by means of symbols. A plurality of signal lines
12
within one component layer extend two-dimensionally from the foreground to the depth direction of the sheet so that signal lines
12
do not actually appear in plurality in the same cross section. In the drawings, however, the plurality of signal lines
12
are represented in parallel within one layer for clarity.
FIG. 14
is a schematic diagram corresponding to a plan view of the uppermost signal layer
9
in
FIGS. 11 and 12
seen from above.
As shown in
FIGS. 12 and 14
, two to three rows starting from the outer side of the rows of signal-related solder bump lands
16
a
are assigned to each signal layer
9
, and signal lines
12
are routed from a projected region
102
c
(see
FIG. 14
) of semiconductor chip
102
outward in one signal layer
9
. Signal line
12
must pass through one of the through holes
15
to be connected to one of the solder balls
106
. While the disposition pitch of the interconnection lines in each component layer is such that the minimum required distance between the outer edges of the interconnection lines is several tens in &mgr;m, the arrangement pitch of through holes
15
is such that the center distance is approximately 800 &mgr;m, which is many times coarser. Therefore, as shown in
FIG. 14
, any given signal line
12
extending outward from projected region
102
c
is routed to the vicinity of the position corresponding to the target solder ball
106
within signal layer
9
, and is connected to the lower layers through via hole
17
and through hole
15
. Since the above given signal line
12
and another signal line
12
extending from a signal-related solder bump
16
a
closer to the inner side must use different through holes
15
, and since cluttering of the interconnection lines should be avoided, a signal line
12
extending from a signal-related solder bump
16
a
closer to the outer side passes through a through holes
15
farther away from projected region
102
c.
On the other hand, signal-related solder bumps
16
a
, not having which signal lines
12
routed outward from projected region
102
c
within signal layer
9
, are connected from this signal layer
9
to a signal layer
9
of a lower layer through via holes
17
. Once the connection reaches the signal layer
9
assigned to the above signal-related solder bumps
16
a
, it is routed in the lateral direction by signal lines
12
.
As shown in
FIGS. 12 and 13
, in this example, the connections from all signal-related bumps are shared by and a
Le Bau T
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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