Semiconductor device

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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Details

C365S225700

Reexamination Certificate

active

07379369

ABSTRACT:
A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode, a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination, a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period, a refresh address generator for generating the refresh address in response to the second control signal, and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core.

REFERENCES:
patent: 6366515 (2002-04-01), Hidaka
patent: 6611470 (2003-08-01), Hidaka
patent: 6947345 (2005-09-01), Takahashi et al.
patent: 2004/0209431 (2004-10-01), Oyu et al.
patent: 2-260195 (1990-10-01), None
patent: 11-126476 (1999-05-01), None
patent: 2002-170387 (2002-06-01), None
patent: 10-1999-0075976 (1999-10-01), None
patent: 10-1999-0085081 (1999-12-01), None
patent: 10-2005-0095980 (2005-10-01), None

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