Semiconductor device

Details Semiconductor device Semiconductor device

2011-03-01

2011-03-01

Zarabian, Amir (Department: 2827)

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C365S154000, C365S156000, C365S189050

Reexamination Certificate

active

07898896

ABSTRACT:
The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.

REFERENCES:
patent: 5701267 (1997-12-01), Masuda et al.
patent: 6181634 (2001-01-01), Okita
patent: 7009246 (2006-03-01), Kawata et al.
patent: 05-074198 (1993-03-01), None
patent: 09-054142 (1997-02-01), None
patent: 2001-023400 (2001-01-01), None

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