Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S903000

Reexamination Certificate

active

07999385

ABSTRACT:
An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

REFERENCES:
patent: 5930163 (1999-07-01), Hara et al.
patent: 6597041 (2003-07-01), Ohbayashi
patent: 6900513 (2005-05-01), Natsume
patent: 6922354 (2005-07-01), Ishikura et al.
patent: 2004/0211993 (2004-10-01), Ootsuka et al.
patent: 2008/0099812 (2008-05-01), Nagata et al.
patent: 2008/0116496 (2008-05-01), Tzeng et al.
patent: 2009/0039408 (2009-02-01), Hatano et al.
patent: 2010/0203672 (2010-08-01), Eun et al.

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