Semiconductor device

Details Semiconductor device Semiconductor device

2011-04-05

2011-04-05

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C438S599000, C257S208000

Reexamination Certificate

active

07919990

ABSTRACT:
A semiconductor device of the present invention comprises an SGT based, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column. A second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column.

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