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Reexamination Certificate

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C365S205000, C365S189090

Reexamination Certificate

active

07983072

ABSTRACT:
In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.

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patent: 7200030 (2007-04-01), Yamaoka et al.
patent: 7403410 (2008-07-01), Burnett
patent: 2-263473 (1990-10-01), None
Digh Hisamoto, et al., “A Folded-channel MOSFET for Deep-sub-tenth Micron Era”, IEDM, IEEE, 1998, 3 Pages.
Xuejue Huang, et al., “Sub 50-nm FinFET: PMOS,” IEDM, IEEE, 1999, 4 Pages.

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