Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-04-06
2000-12-19
Tran, Minh Loan
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257300, 257306, 257309, H01L 27108, H01L 2976, H01L 2994, H01L 31119
Patent
active
061630438
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device and, more particularly, to improvements in variations in characteristics and characteristic deterioration in a ferroelectric memory device.
BACKGROUND ART
As conventional semiconductor devices, there have been developed various circuits from relatively small-sized integrated circuits mounting, for example, an amplifier circuit, an oscillating circuit, a power supply circuit and the like, to relatively large-sized integrated circuits, such as a microprocessor and a memory device. Especially in recent years, as a kind of non-volatile memory device, a ferroelectric memory device with ferroelectric capacitors as capacitors constituting memory cells has been contrived.
The ferroelectric capacitor consists of a pair of electrodes opposite to each other, and a dielectric layer comprising a ferroelectric material and sandwiched between both electrodes, and has the hysteresis characteristic as a relationship between a voltage applied between the both electrodes and polarizability of the ferroelectric material. That is, the ferroelectric capacitor has a construction in which even when the electric field (applied voltage) is zero, a remaining polarization of a polarity in accordance with the hysteresis of voltage application remains in the ferroelectric layer, and in the ferroelectric memory device non-volatility of the storage data is realized by representing storage data by the remaining polarization of the ferroelectric capacitor.
In a non-volatile memory device using such ferroelectric capacitors, it is an important objective to reduce variations in the hysteresis characteristics of the ferroelectric capacitors and reduce changes in the hysteresis characteristic accompanying the use.
More specifically, FIGS. 14 to 16 are diagrams for explaining a conventional ferroelectric memory device, FIG. 14 is a plan view illustrating a memory cell array in the ferroelectric memory device, FIG. 15 is a cross-sectional view along a line XV--XV portion in FIG. 14, and FIG. 16 is a plan view illustrating a position relation between upper electrodes and a lower electrode of ferroelectric capacitors.
In the figures, reference numeral 200 designates a memory cell array constituting a ferroelectric memory device, a plurality of transistor regions 220a are arranged on a silicon substrate 201 in a first direction D1, and an insulating film 202 for element isolation is formed on a portion of the silicon substrate 201, except the transistor regions 220a.
On both sides of the transistor regions 220a in a line along the first direction D1, lower electrodes (first electrodes) 211 are formed as cell plate electrodes on the insulating film 202 for element isolation via first interlayer insulating films 203. The lower electrode 211 comprises a metallic material, such as titanium and platinum, and has a stripe-shaped plan configuration extending along the first direction D1. On surfaces of the lower electrodes 211, ferroelectric layers 213 are formed.
On the ferroelectric layers 213 on the surfaces of the lower electrodes 211, upper electrodes (second electrodes) 212 comprising a metallic material, such as titanium and platinum, are formed corresponding to the respective transistor regions 220a. That is, on the ferroelectric layers 213, the plurality of upper electrodes 212 are arranged along the first direction D1. A plan shape of each upper electrode 212 is a rectangular shape having the first direction D1 as its longitudinal direction, and as is known from FIG. 14, the area of each upper electrode 212 is smaller than that of the lower electrode 211. Here, ferroelectric capacitors 210 are constituted by the lower electrode 211, the upper electrodes 212, and the ferroelectric layer 213 located between these electrodes, and the surfaces of the ferroelectric layers 213 and the surfaces of the upper electrodes 211 are covered with second interlayer insulating films 204.
In this case, the upper electrode 212 is disposed in a center portion of the lower electrode 211, and
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Hirano Hiroshige
Takeo Masato
Matsushita Electronics Corp.
Nguyen Cuong Quang
Tran Minh Loan
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