Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-26
2001-12-04
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S390000, C365S185040, C365S185030, C365S185140
Reexamination Certificate
active
06326661
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body having a region of a first conductivity type adjoining a surface of the semiconductor body, which semiconductor body is provided at the surface with a non-volatile memory cell comprising a source and a drain of an opposite, second conductivity type provided in the semiconductor body, between which source and drain the surface of the semiconductor body is provided with a floating gate and a select gate, the floating gate and the select gate both having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having side-wall portions extending substantially transversely to the surface of the semiconductor body, above which floating gate a control gate is situated, which control gate overlaps the select gate.
Such a non-volatile memory cell, which is often referred to as an EEPROM (Electrically Erasable Programmable Read-Only Memory) cell, comprises at least one select transistor and a field-effect transistor with floating gate, also referred to as floating gate transistor.
A semiconductor device of the kind mentioned in the opening paragraph is known from EP-A-763 856. In the known semiconductor device the control gate stretches out over the select gate to substantially beyond the side-wall portion of the select gate facing away from the floating gate.
A disadvantage of the known semiconductor device is that the size of the memory cell is large owing to the fact that the control gate extends out to substantially beyond the sidewall portion of the select gate facing away from the floating gate. As a consequence, the density of memory cells in a non-volatile memory of a given size is small. In addition, parasitic capacitances are induced between the control gate and the select gate as a result of the closeness between the control gate and the select gate during operation of the memory cell, which parasitic capacitances adversely increase the RC time of the select gate. Moreover, it is not possible to subject the select gate of the memory cell to a self-aligned silicide process, also referred to as salicide process, to reduce its sheet and contact resistance. Hence, the resistance of the select gate is large, which also adversely influences the RC time of the select gate.
SUMMARY OF THE INVENTION
The invention has inter alia for its object to provide a semiconductor device of the kind mentioned in the opening paragraph, which semiconductor device provides a large capacitive coupling between the control gate and the floating gate of the memory cell while counteracting the above-mentioned disadvantages.
According to the invention, this object is achieved in that the control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the side-wall portions of the floating gate facing the source and the drain, and ends above the substantially flat surface portion of the select gate. These measures provide a semiconductor device having a large capacitive coupling between the control gate and the floating gate of the memory cell and counteracting the above-mentioned disadvantages. Since the control gate ends above the substantially flat surface portion of the select gate, the size of the memory cell is smaller. As a consequence, the density of memory cells in a non-volatile memory of a given size is larger. Moreover, the parasitic capacitances between the control gate and the select gate are smaller, which decreases the RC time of the select gate. As the select gate is not entirely covered with the control gate, the select gate can be partially subjected to the earlier-mentioned self-aligned silicide process in order to reduce its resistance and, hence, its RC time.
A preferred embodiment of the semiconductor device in accordance with the invention is characterized in that a substantial part of the substantially flat surface portion of the select gate is left free. As a consequence, the parasitic capacitances between the control gate and the select gate are reduced, and a larger area of the select gate can be subjected to the above-mentioned self-aligned silicide process, which reduces the resistance of the select gate. Both effects further decrease the RC time of the select gate.
If the memory cell comprises one select gate, which memory cell is also referred to as two-transistor (2T) cell, the select gate is advantageously provided at the side of the floating gate adjacent to the source. Since a select transistor needs to switch through a lower programming voltage when provided at the side of the source than when provided at the side of the drain, it can be processed with a thinner gate oxide, for example the same gate oxide as applied for adjacent floating gate transistors, which enables the use of a smaller channel length to avoid punch-through.
Although the invention is applicable to a stand-alone non-volatile memory, special advantages are obtained for a non-volatile memory embedded in a CMOS or BICMOS integrated circuit, as smaller memory cells can be manufactured without an increase in the CMOS or BICMOS process complexity.
Further advantageous embodiments of the semiconductor device in accordance with the invention are described in other dependent claims.
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Dormans Guido J. M.
Verhaar Robertus D. J.
Flynn Nathan
Forde Remmon R.
U.S. Philips Corporation
Waxler Aaron
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