Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2000-07-11
2001-02-27
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S230050, C365S230090
Reexamination Certificate
active
06195294
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and particularly to a semiconductor device which includes a highly-integrated memory and multiple processing elements formed on a single chip and is suitable for data processing.
Semiconductor devices which include a processor and memory mounted on a circuit board and are used as a specialized processing system for implementing high-speed processing, such as image processing, of a vast amount of data are shown in the prior art. This prior art, in which the processor and memory are connected through buses, necessitates the operation of bus arbitration. Thus, when a series of read, compute and write operations is repeated for a vast amount of data, a significant amount of time is expended for the read and write operations and their switching operation, and data processing is inefficient.
An improved semiconductor device which includes multiple processing elements and a memory cell array mounted on a single chip, and operates to read out data of memory cells on a word line of the memory cell array and compute the data in parallel has been shown in the Prior Art. A semiconductor device of this type is described for example in the publication: Y.Aimoto, et al. “Memory Array Circuits of Integrated Memory Array Processor (IMAP) LSI”, Proceeding of the 1994 IEICE Spring Conference,5-261 C-693.
This prior art device includes 64 processing elements and SRAMs of 2 Mb integrated on a chip, and is designed to operate the processing elements in parallel in response to an instruction based on the SIMD (Single Instruction Stream Multiple Data Stream) scheme. Although the computation of image data processing is not very intricate, the same computation is repeated a great number of times for a vast amount of data.
When the above-mentioned semiconductor device having multiple processing elements and a memory cell array is used for image data processing, the operations of reading out data from memory cells, implementing certain computation for the data with the SIMD-based processing circuit and writing data of computation result to memory cells are repeated. The series of read, compute and write operations of data takes an amount of time which is the sum of the read time tr, computation time tc and write time tw, and an m-time repetition of this series of operations takes a total time of m(tr+tc+tw).
The computation time tc may be reduced to reduce in the future when the processing circuit is further sped up based on more advanced scaling achieved by the progress of semiconductor fabricating technology.
However, the above-mentioned prior art semiconductor device having multiple processing elements and a memory cell array integrated on a chip will encounter the difficulty of increasing the volume of signals from memory cells contrary to the enhanced scaling of the memory cell array as opposed to the speeding up of processing circuit. Therefore, the data read time tr and write time tw will not be reduced significantly. Accordingly, the speed of repetitive image data processing, in which data are read out of memory cells, data are computed and data of computation result are written back to the same memory cells, will be unfavorably dominated by the data read time tr and write time tw.
SUMMARY OF THE INVENTION
Accordingly, the present invention is intended to overcome the foregoing deficiency in the prior art, and its prime object is to provide a semiconductor device which is capable of speeding up the data processing including repetitive computations such as image data processing and also reducing power consumption.
Another object of the present invention is to provide a versatile semiconductor device which can be used not only as an image data processor, but also as a usual memory for the main memory of a system, or partly for an image data processor and partly for a usual memory.
In order to achieve the above objectives, the present invention resides in a semiconductor device integrated on a chip, the device including a memory cell array having a plurality of memory cells located at intersections of data lines and word lines, a decoder which selects at least one of the word lines for reading out data from memory cells of the memory cell array onto data lines that intersect the selected word line, at least one processing element, a data transfer circuit which transfers data between the processing element and the memory cell array, and a control circuit which controls at least the data transfer circuit, decoder and processing element, wherein the data transfer circuit has read paths and write paths that operate independently of each other so that a write operation to a part of the data lines that intersect the selected word line and a read operation from another part can take place at least partially concurrently.
According to the inventive semiconductor device, the data transfer circuit is capable of concurrently transferring data read out of the memory cell array to the processing element and output data of the processing element to the memory cell array by having separate read paths and write paths between the memory cell array and the processing element. Based on the independent read paths and write paths, it is possible for the device to carry out the read operation and write operation partially concurrently by selecting different data lines between the memory cell array and processing element. Accordingly, in repetitive operations of reading out data from memory cells, computing the data and storing data of computation result in the memory cells, data can be read out and written concurrently through read paths and write paths. Consequently, the time expended for an m-time repetition of a series of operations can be reduced from the conventional m(tr+tc+tw) to tr+m×tc+tw for example by implementing the data reading and writing within the computation time tc.
In this semiconductor device, the data transfer circuit can include data reading means which selects a certain number of data lines among all data lines and reads data out of memory cells to the processing element over the selected data lines, and data writing means which selects independently of the data reading means a certain number of data lines among all data lines and writes output data of the processing element to memory cells over the selected data lines.
The data reading means is formed of switching means located between the read paths and data lines and controlled by the signals from the control circuit, and the data writing means can be formed of switching means located between the write paths and data lines and controlled by the signals from the control circuit. The switching means located between the read paths and data lines operate in response to the signals from the control circuit to connect the read paths to the data lines so that readout data on the selected data lines are delivered to the processing element. The switching means located between the write paths and data lines operate in response to the signals from the control circuit to write the computation result of the processing element to the memory cells over the selected data lines.
The data transfer circuit is preferably formed of data line blocks each including a certain number of data lines divided from all data lines, a read path or a pair of read paths and a write path or a pair of write paths provided for each block, and switch means each provided between a data line of each block and the read path and write path of the block and controlled by the control circuit to connect the data line to the read path, or connect the data line to the write path, or have an open state. This arrangement enables the connection of a data line of a block to a read path so that data is read out of a memory cell and, at the same time, the connection of a data line of the same block to a write path so that the computation result of the processing element is written to a memory cell.
Alternatively, the data transfer circuit has its blocks each further divided in
Ayukawa Kazushige
Nakagome Yoshinobu
Watanabe Takao
Hitachi , Ltd.
Hoang Huan
Mattingly Stanger & Malur, P.C.
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