Semiconductor device

Details Semiconductor device Semiconductor device

2000-05-01

2001-10-02

Clark, Sheila V. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000

Reexamination Certificate

active

06297545

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a resin-sealed type semiconductor device having an LOC (Lead On Chip) structure and, more particularly, to a technique which is effective when applied to a thin,small-sized semiconductor package having a TSOP (Thin Small Outline Package) structure or the like.
A typical resin-sealed type semiconductor device having an LOC structure comprises, as shown in
FIG. 22
(see Japanese Patent Laid-Open No. 2-246125/1990), for example, a semiconductor chip
1
including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate; a plurality of leads,each including an inner lead portion
3
A comprising inner leads
3
A
1
forming signal inner leads (a first region) and a common inner lead
3
A
2
for supplying a power voltage and a reference voltage (a second region: hereinafter referred to as the bus-bar leads or fixed potential leads), and an outer lead portion
3
B formed integrally with the inner lead portions
3
A; bonding wires
5
for electrically connecting the external terminals (pads) and the signal inner leads
3
A
1
and the bus-bar leads
3
A
2
of the inner lead portions
3
A, respectively; and a sealer
2
A for sealing the semiconductor chip
1
, the inner lead portions
3
A and the bonding wires
5
. The signal inner leads
3
A
1
and the bus-bar leads
3
A
2
are arranged over the major face of the semiconductor chip
1
, being separated therefrom by an insulating film
4
, and the bus-bar leads
3
A
2
are arranged substantially in parallel with the major face of the semiconductor chip
1
.
SUMMARY OF THE INVENTION
First, a description will be presented of the items which have not been disclosed in the publicly-known document (Japanese Patent Laid-Open No. 2-246125/1990) and have been investigated by the present inventor.
When a resin-sealed type semiconductor device having an LOC structure, as shown in
FIG. 22
, is applied as it is to a thin small-sized semiconductor package (TSOP), as shown in FIGS.
23
and
24
(
a
), the entire package becomes thin (e.g., 1.0 mm), so that the resin over the inner leads
3
A
1
accordingly becomes as thin as 0.195 mm. This makes it necessary to set the loop heights of the wires
5
at small values. However, in doing this, the bonding wires
5
and the bus-bar leads
3
A
2
of the signal wires may contact, causing a short circuit, and this problem makes it difficult to reduce the thickness of the resin. When the wire loop heights must be suppressed to low levels, a contrivance in which an insulating coating material
20
is applied to the bus-bar leads
3
A
2
is needed.
Reference will be made to the schematic construction of
FIG. 23
(a top plan view of a resin-sealed type semiconductor device having a TSOP structure) and to the examples of FIG.
24
(
a
) to FIG.
24
(
c
) (a section of the device of FIG.
23
). In this resin-sealed type semiconductor device having a TSOP structure, to a face of a semiconductor substrate of a semiconductor chip
1
(hereinafter referred to as the “major face of the semiconductor chip
1
”), where a circuit and a plurality of external terminals are formed, inner lead portions
3
A, which include a plurality of signal line inner leads
3
A, and the bus-bar leads
3
A
2
, which have an insulating coating material
20
applied to their upper faces, are fixed through the insulating film
4
. The inner lead portions
3
A and the outer lead portions
3
B are formed integrally to constitute leads
3
.
As shown in FIGS.
23
and FIGS.
24
(
a
) to
24
(
c
), the signal line inner leads
3
A
1
and the bus-bar leads
3
A
2
, which have the insulating coating material
20
applied to their upper faces, of the inner lead portions
3
A, are arranged over the major face of the semiconductor chip
1
and are spaced therefrom by the insulating film
4
, and the bus-bar leads
3
A
2
are arranged substantially in parallel with the major face of the semiconductor chip
1
.
The plurality of signal inner leads
3
A
1
, the bus-bar leads
3
A
2
and the semiconductor chip
1
are electrically connected through the bonding wires
5
and are sealed with a mold resin (the sealing body)
2
A. The thin type package
2
thus sealed is shaped by cutting the suspension leads (chip supporting leads)
3
C and the outer lead portions
3
B from the lead frame.
In a thin small-sized semiconductor package with a TSOP structure), which has been investigated by the present inventor, the mold resin
2
A over the semiconductor chip
1
is thin, as shown in FIG.
24
(
a
), so that problems arise, such as an appearance defect in which the bonding wires
5
,such as Au wires,are seen through the upper face of the package, and a problem of exposure of the wire themselves to the outside. If this thickness is made even smaller (to about 0.5 mm), as shown in FIG.
24
(
b
), the appearance defect and the wire exposure problem become more critical.
Another problem is that when the mold resin (the sealing body)
2
A over the major face of the semiconductor chip is thin, cracks are likely to occur, thereby deteriorating the reliability.
In order to lower the wire loops, as shown in FIG.
24
(
c
), it is conceivable to eliminate the insulating tape
4
and to fix the signal inner leads
3
A
1
and the bus-bar leads
3
A
2
to the major face of the semiconductor chip
1
directly with an adhesive. If the distances (spacings) between the major face of the semiconductor chip
1
and the signal inner leads
3
A
1
become short, however, the parasitic capacitance between the major face of the semiconductor chip
1
and the signal inner leads
3
A
1
increases to create a problem wherein the electric characteristics may become deteriorated.
An object of the invention is to provide a technique which is capable of thinning the semiconductor package without causing deterioration of the electric characteristics thereof.
Another object of the invention is to provide a technique which is capable of suppressing the parasitic capacitance between the major face of the semiconductor chip and the leads even if the semiconductor package is thinned.
Another object of the invention is to provide a technique which is capable of ensuring a proper thickness of the sealer over the semiconductor chip of the semiconductor package even if the overall thickness of the semiconductor package is reduced.
Another object of the invention is to provide a technique which is capable of balancing the quantities of the upper and lower sealers of the semiconductor chip even if the overall thickness of the semiconductor package is reduced.
The foregoing and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
of the features to be disclosed herein. representative ones will be briefly summarized in the following.
(1) A semiconductor device has a semiconductor chip including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate, a plurality of leads each including an inner lead portion and an outer lead portion formed integrally with the inner lead portion, bonding wires electrically connecting the external terminals and the inner lead portions, respectively, and a sealing body for sealing the semiconductor chip, the inner lead portions and the bonding wires, wherein the inner lead portions are arranged over the major face of the semiconductor chip at predetermined spacings between the major face and the inner leads, and the portions of the inner leads arranged over the major face are thinner than the other portions of the inner leads.
(2) In a resin-sealed type semiconductor device according to the aforementioned paragraph (1), the portions, arranged over the major face of the semiconductor chip, of the inner lead portions are fixed at their leading end portions to the major face of the semiconductor chip through an insulating film.
(3) In a resin-sealed type semiconductor device according to the aforementioned paragraph (1), the porti

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