Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-01-30
2001-10-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S659000, C257S660000
Reexamination Certificate
active
06303982
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a technology effective if applied to the package of a large-scale integrated circuit of high integration.
In the prior art, the semiconductor chip is sealed up with a molding resin so that it may be protected. Several methods are used to mount leads in position on the semiconductor chip before the sealing.
For example, a lead frame having tabs at its center is used and mounted before the semiconductor chip is sealed. In this prior art, there is known a method of connecting electrode pads around the semiconductor chip with the corresponding inner leads through bonding wires.
The common problem among the semiconductor packages of the prior art is that the metal lead frame is cracked along the mold parting lines providing the exits of the lead lines.
Another problem is that the passages for moisture or contaminants in the atmosphere to steal along the metal lead wires from the outside into the semiconductor chip are relatively short.
Moreover, the surface mounting type package is seriously troubled by the so-called “reflow cracking” problem that the moisture contained in the package is expanded by the heat of the solder reflow to crack the package.
Still another problem is that the bonding wires necessary for connecting the inner leads with the electrode pads of the semiconductor chip cannot be intersected partly because they are relatively long and partly because they are alternately assigned to input/output terminals.
In order to solve the above-specified problems, therefore, there has been proposed in Japanese Patent Laid-Open No. 241959/1986 (corresponding to E.P. Publication No. 0198194) a semiconductor device in which a plurality of inner leads are adhered to the circuit forming surface of a semiconductor chip through the semiconductor chip and insulating films by an adhesive, in which the inner leads and the semiconductor chip are electrically connected through bonding wires and in which common inner leads (or bus bar inner leads) are disposed in the vicinity of the longitudinal center line of the circuit forming surface of the semiconductor chip.
Also disclosed in Japanese Patent Laid-Open No. 167454/1985 or 218139/1986 (corresponding to U.S. Ser. No. 345,332) is the package structure of the so-called “tabless lead frame type”, in which the tabs (i.e., the die pads) mounting the chip are eliminated to mount the chip on the insulating films adhered to the leads (i.e., Chip On Lead) and in which the bonding pads of the chip and the leading ends of the leads are connected through wires.
Also proposed in Japanese Patent Laid-Open No. 92556/1984 or 236130/1986 is the package structure in which the leads are adhered to the upper surface of the chip (i.e., Lead On Chip) by an adhesive and in which the bonding pads of the chip and the leading end portions of the leads are connected through wires. According to the above-specified package structure arranged with the leads on the upper or lower surface of the chip, the heat and moisture resistances of the package can be improved because the leads in the package can be elongated. Thanks to the elimination of the tabs, moreover, the contact between the resin and the leads is improved to improve the reflow cracking resistance. As a result, even the large-sized chip can be packed in the package of the existing size. Moreover, this package structure is advantageous in reducing the wiring delay because it can shorten the bonding wires.
SUMMARY OF THE INVENTION
We have investigated the aforementioned semiconductor devices of the prior art and have found the following problems:
(1) In the semiconductor device of the prior art, the inner leads are adhered to the circuit forming surface of the semiconductor chip through the semiconductor chip and the insulating films by the adhesive. Because of the large stray capacity between the inner leads and the semiconductor chip, the semiconductor device has a problem that the signal transmission rate is dropped by the large stray capacity to increase the electrical noises.
(2) Because of the large area of the insulating films, the amount of moisture absorbed is increased so that the absorbed moisture is gasified and expanded in the package during the reflow, thus causing a problem that the package cracking is established by the moisture expansion.
(3) Since the aforementioned insulating films are made of a resin of polyimide, the amount of absorbed moisture is increased so that the absorbed moisture is gasified and expanded in the package during the reflow, thus causing the problem of package cracking.
(4) Since the aforementioned adhesive is made of an acrylic resin, it is degraded by the pressure cracker test or the like, thus raising a problem that the reliability is dropped by the electrical leakage between the leads and the corrosions of the aluminum electrodes.
(5) Since the circuit forming surface of the semiconductor chip is not coated all over with the resin coating of polyimide for protections against alpha rays, there arises a problem that errors are caused by the alpha rays.
(6) The common inner leads (i.e., bus bar inner leads) are used as radiating plates, but the element having a large exothermic portion is not covered all over with the inner leads. There arises a problem that the radiation is insufficient in an element of 1 watt or higher.
(7) Since the insulating films made of the aforementioned resin of polyimide has a large area, there arises a problem that the semiconductor device is weak in the temperature cycle.
(8) The wire bonding is accomplished across the aforementioned mentioned inner leads (i.e., bus bar inner leads), thus raising a problem in poor productivity.
(9) The aforementioned adhesive layer is so soft that the wire bonding conditions are difficult to set, thus raising the problem of poor productivity.
(10) This problem of poor productivity is also caused by the poor workability for mounting the insulating films on the semiconductor chip.
(11) Since the semiconductor chip is insufficiently fixed by the portions of the inner leads, it is moved in the resin sealing (or molding) operation, thus raising a problem that the productivity is poor.
An object of the present invention is to provide a technique for improving the reliability of a semiconductor device.
An object of the present invention is to provide a technique for a semiconductor device to improve the signal transmission rate due to the stray capacity between the semiconductor chip and the leads and to reduce the electrical noises.
Another object of the present invention is to provide a technique for a semiconductor device to improve the radiating efficiency of the heat generated.
Another object of the present invention is to provide a technique for a semiconductor device to reduce the influences of the heat during the reflow.
Another object of the present invention is to provide a technique for a semiconductor device to reduce the influences of the heat in the temperature cycle.
Another object of the present invention is to provide a technique for a semiconductor device to prevent the molding defects from being caused.
Another object of the present invention is to provide a technique for a semiconductor device, which has a package structure arranged with leads on the upper or lower surface of the chip, to reduce the parasitic capacity to be established between the chip and the leads.
Another object of the present invention is to provide a technique for a semiconductor device to improve the productivity.
Another object of the present invention is to provide a technique to improve the moisture resistance.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the invention to be disclosed herein will be briefly described in the following:
1. A semiconductor device of the type, in which common inner leads are adhered to the vicinity of the center line taken
Anjo Ichiro
Eguchi Syuuji
Hasebe Akio
Hozoji Hiroshi
Ichitani Masahiro
Antonelli Terry Stout & Kraus LLP
Clark Sheila V.
Hitachi , Ltd.
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