Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-06-11
2001-01-30
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S647000
Reexamination Certificate
active
06181018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same.
2. Description of the Related Art
In a manufacturing process of semiconductor devices, a plurality of patterns, such as an active region, an electrode, etc., are formed one after another. Thus, in a semiconductor device, a mask which has a pattern to be formed after a-previously-formed pattern needs to be arranged in an appropriate position.
For example, in a lithography process, a photomask is aligned in a predetermined position by using an alignment mark, which is formed on a semiconductor substrate. Specifically, laser is applied to the alignment mark, such as a diffraction grating or the like. In order to detect the alignment mark, a waveform of diffracted light is used, thereby the photomask can be arranged.
As the semiconductor device fabrication process becomes more and more complicated, it is difficult to retain the alignment mark in a desired state. For example, if the diffraction grating is used as the alignment mark, a film formed on the alignment mark tends to remain thereon, when patterning the film. Therefore, the form of the alignment mark may not desirably be retained.
In a case where a trench which has been made for performing shallow trench isolation (a technique for electronically isolating elements on the semiconductor substrate, by forming a trench and filling the trench with insulating materials) is used as an alignment mark, it is still difficult to retain the desirable form of the alignment mark. When a gate electrode is formed, a polycide is to be formed on the semiconductor substrate with the alignment mark. The gate electrode is formed by patterning the polycide by performing photolithography. In patterning the polycide, anisotropic etching is performed thereto. If the polycide is formed in the trench, the polycide may not completely be removed therefrom by the anisotropic etching, owing to the depth of the trench (alignment mark) for the shallow trench isolation. The amount of each polycide remaining in the trench may vary, because an etching rate of the anisotropic etching varies. That is, the form of the alignment mark may not preferably be retained after the formation of the gate electrode.
If the form of the alignment is not retained desirably, the alignment of subsequent mask may become inaccurate. As a result, the semiconductor device may be manufactured with a low degree of reliability, and the yield of such semiconductor devices is low.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a manufacturing method capable of improving an yield of semiconductor devices.
Another object thereof is to provide a semiconductor device with a high degree of reliability.
Further object thereof is to provide a semiconductor device having an alignment mark which enables to improve alignment accuracy, and to provide a manufacturing method of the same.
In order to achieve the above-described objects, according to the first aspect of the present invention, there is provided a semiconductor device comprising:
a substrate having a surface area on which a plurality of elements are formed; and
an oxide which is formed on the substrate, and which has a portion smoothly protruding from a surface of the substrate, and which forms a step as an alignment mark.
According to the present invention, patterning of wiring, etc., can be performed with a high degree of accuracy.
The oxide may be formed in a trench.
The trench may have a shallow trench isolation structure.
The oxide may form a step smaller than the trench.
With the above-described structures, formation of the step may be easily and preferably retained. As a result, alignment accuracy can be improved, and a semiconductor device with a high degree of reliability can be manufactured.
The step may include a sidewall having inclination gentler than a taper angle of the trench.
With such structures also, the formation of the step may be easily and preferably retained. Thus, the alignment accuracy can be improved, and the semiconductor device having a high degree of reliability can be manufactured.
The step may be in a range between 50 nm and 100 nm in height.
The semiconductor device may further include on the substrate and the oxide an electrode which comprises polysilicon and silicide, or metal.
According to the second aspect of the present invention, there is provided a manufacturing method of a semiconductor device comprising:
forming a first oxide and a nitride on a substrate;
patterning the nitride and the first oxide to expose an underlying portion of the substrate;
forming a trench in the substrate by using the nitride as a mask;
filling the trench with a second oxide;
making a oxide thickness difference between an alignment mark region and other areas; and
forming a step as an alignment mark, by protruding a portion of the second oxide from the surface of the substrate by removing the nitride, the first oxide, and at least a portion of the second oxide.
According to the present invention, patterning of wiring, etc., can be performed with a high degree of accuracy.
The step height is smaller than a depth of the trench.
The forming the step may include forming a step in a range between 50 nm and 10 nm in height.
The forming the step may include forming a step having a sidewall with inclination gentler than a taper angle of the trench.
The making the oxide thickness difference may include:
planarizing the second oxide to expose the surface of the nitride, so that the second oxide has substantially same height as the nitride;
covering the second oxide of the alignment mark with a photoresist; and
etching the second oxide in an uncovered region to a predetermined thickness.
The planarizing may include:
removing the second oxide by CMP (Chemical Mechanical Polishing) using the nitride as a stopper.
The etching the second oxide may include etching the second oxide in an uncovered region in a range between 50 nm and 100 nm.
The forming the step may include removing the nitride, the first oxide, and the at least a portion of the second oxide by performing isotropic etching.
The manufacturing method of the semiconductor device may further include:
forming a conductive film in the area including the step on the substrate;
aligning a photomask by using a step of the conductive film as an alignment mark, the step of the conductive film being shaped in accordance with a shape of the step; and
patterning the conductive film.
The forming the conductive film may include forming the conductive film with polysilicon and suicide, or with metal.
The patterning the conductive film may include patterning the conductive film by performing anisotropic etching.
Other advantages and meritorious features of the present invention will become more fully understood from the preferred embodiments, the claims, the drawings, and the brief description of which follows.
REFERENCES:
patent: 6010945 (2000-01-01), Wu
patent: 6015744 (2000-01-01), Tseng
patent: 61-154126 (1986-07-01), None
patent: 62-112325 (1987-05-01), None
patent: 2-77111 (1990-03-01), None
patent: 2-222519 (1990-09-01), None
Jr. Carl Whitehead
NEC Corporation
Potter Roy
Scully Scott Murphy & Presser
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