Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
1997-11-19
2001-05-01
Fahmy, Wael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S774000
Reexamination Certificate
active
06225686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package having such a structure that a package substrate and a semiconductor chip are coupled to each other.
2. Description of Related Art
A COX (Chip On X) structure in which a bare semiconductor chip is directly mounted on a wiring board has been generally known as a semiconductor package structure using a bare technique. The COX structure is mainly classified into a structure based on a flip chip bonding technique and a structure based on a wire bonding technique.
FIGS. 1A and 1B
show a conventional semiconductor package structure based on the flip chip bonding technique. More specifically,
FIG. 1A
is a cross-sectional view of the semiconductor package structure, and
FIG. 1B
is a plan view of the semiconductor package structure.
In the semiconductor package shown in
FIGS. 1A and 1B
, a semiconductor chip
51
is put face down on a package substrate
50
serving as a base. A bump
52
serving as a chip electrode is formed on the surface (the lower surface in the figures) of the semiconductor chip
51
, and the semiconductor chip
51
and the package substrate
50
are electrically and mechanically connected to each other through the bump
52
. Further, a wiring pattern
53
is formed on the chip-mounted surface (the upper surface in the figures) of the package substrate
50
, and an embedded through hole is formed at the pattern end portion of the wiring pattern
53
.
According to the package structure as described above, even when the size of the semiconductor chip
51
is varied, the same-size package substrate
50
may be used commonly to these semiconductor chips having different sizes by forming the wiring pattern
53
in accordance with the chip size of each semiconductor chip.
FIG. 2
is a cross-sectional view showing the conventional structure of a semiconductor package based on the wire bonding technique.
In the semiconductor package shown in
FIG. 2
, a semiconductor chip
61
is put face up on a package substrate
60
serving as a base. A chip electrode (not shown) is formed on the surface of the semiconductor chip
61
, and the chip electrode is electrically connected to an embedded through hole electrode
63
of the package substrate
60
through a wire
62
such as a metal wire or the like.
In the package structure, even when the size of the semiconductor chip
61
is varied, the same-size package substrate
60
may be used commonly to these semiconductor chips having different sizes by performing wire bonding in accordance with the chip size.
However, the conventional semiconductor package has the following problems.
First, in the case of the semiconductor package shown in
FIG. 1
, the electrode position (bump position) is varied in accordance with the size of the semiconductor chip
51
. Therefore, when semiconductor chips
51
having the same number of electrodes are mounted, for example when a semiconductor chip
51
which is smaller in size than described above as shown in
FIG. 3A
is mounted, a package substrate
50
having a wiring pattern
53
which is matched with the semiconductor chip
51
must be prepared. Accordingly, even when semiconductor chips
51
have the same number of electrodes, a package substrate
50
which is exclusive to each size of semiconductor chip must be prepared, and it greatly obstructs standardization of parts.
Further, in the case of the semiconductor package shown in
FIG. 2
, the bonding length which is required to keep proper wire bonding quality, that is, a fixed permissible range is given to the horizontal distance BL between the bonding position at the chip side and the bonding position at the substrate side. Therefore, if the horizontal distance exceeds the permissible range, for example when the bonding length BL is excessively short as compared with the chip size shown in
FIG. 3B
, the wire
63
comes into contact with the chip edge to induce a short-circuit failure. Conversely, when it is excessively long, there occurs such a disadvantage that the wire
62
is hung down. Accordingly, a limitation is imposed on the chip size of semiconductor chips which can be mounted on the same-size package substrate
60
. Further, when inner coat agent
64
having a large contraction rate is provided as show in
FIG. 3C
, the wire
62
is greatly deformed due to the contraction of the inner coat agent in the progress of the hardening of the inner coat agent, so that a limitation is also imposed on selection of materials.
In addition, each of the semiconductor packages shown in
FIGS. 1A and 1B
and
FIG. 2
has such a structure that the semiconductor chip
51
(
61
) is mounted on the package substrate
50
(
60
), and thus the thickness of each part is added, so that the total thickness of the overall package is large. Accordingly, these semiconductor packages cannot support a compact and low-profile design for semiconductor packages which will be required in the future.
SUMMARY OF THE INVENTION
A first object of the present invention is to implement a compact and low-profile design for semiconductor packages.
A second object of the present invention is to standardize package substrates of semiconductor packages.
In order to attain the above object, a semiconductor device according to the present invention includes a semiconductor chip having plural electrode pads at the peripheral edge portion thereof, a frame-shaped package substrate in which the semiconductor chip is mounted and which has plural electrode portions corresponding to the respective electrode pads, a lead terminal for connecting each of the electrode pads of the semiconductor chip and the corresponding electrode portion of the package substrate, and sealing resin for sealing the semiconductor chip.
In the above-described semiconductor device, the semiconductor chip is mounted in the frame of the frame-shaped package substrate, and thus the thickness of the overall package can be reduced by the amount corresponding to the thickness of the semiconductor chip as compared with the prior art.
Further, a semiconductor device manufacturing method according to the present invention includes a first lead connecting step of connecting a lead terminal to each of plural electrode pads of a semiconductor chip which has the plural electrode pads at the chip peripheral edge portion while setting a lead connection angle in accordance with the chip size, a lead cutting step of cutting the lead terminal by a predetermined length in accordance with an electrode forming position of the frame-shaped package substrate on which the semiconductor chip can be mounted, a second lead connecting step of connecting the cut portion of the lead terminal to the electrode portion of the package substrate while the semiconductor chip is mounted on the package substrate, and a resin sealing step of sealing the semiconductor chip mounted on the package substrate with sealing resin.
According to the semiconductor device manufacturing method, in the first lead connection step, each lead terminal is connected to each electrode pad while keeping the lead connection angle in accordance with the size of the semiconductor chip, and in the subsequent lead cutting step the lead terminal is cut by a predetermined length in accordance with the electrode forming position of the package substrate. Therefore, each of semiconductor chips which are different in size can be mounted on each of common package substrates with no trouble by merely changing the lead connection angle in the first lead connecting step and the lead cutting length in the lead cutting step in accordance with the size of each of various semiconductor chips.
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patent: 4251852 (1981-02-01), Ecker et al.
patent: 5130889 (1992-07-01), Hamburgen et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5258647 (1993-11-01), Wojnarowski et al.
patent: 5409865 (1995-04-01), Karnezos
patent: 5561323 (1996-10-01), Andros et al.
patent: 5583377 (1996-12-01), Higgins, III
patent: 5814883 (1998-09-0
Fahmy Wael
Potter Roy
Sonnenschein Nath & Rosenthal
Sony Corporation
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