Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-07
2001-09-11
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S057000, C257S069000
Reexamination Certificate
active
06288429
ABSTRACT:
This application is a 35 U.S.C. §371 filing of International Patent Application No. PCT/JP97/04344, filed Nov. 27, 1997. This application claims priority benefit of Japanese Patent Application No. 8-324465, filed Dec. 4, 1996.
TECHNICAL FIELD
The present invention relates to a semiconductor device in the form of a transistor which operates at a low power supply voltage by dynamically changing a threshold, and a semiconductor device incorporating such a transistor. The present invention also relates to a device separation technique suitable for integration of such semiconductor devices.
BACKGROUND ART
In a CMOS circuit (a complementary circuit), the power consumption is proportional to the square of the power supply voltage. Therefore, it is effective to reduce the power supply voltage for reducing the power consumption of a CMOS LSI. However, as the power supply voltage is reduced, the driving power of the transistor decreases, thereby posing a problem of an increase in the delay time of the circuit. This problem becomes more significant the more the power supply voltage is reduced. Particularly, it has been known that the increase becomes significant when the power supply voltage is three times the threshold or less.
A possible way to improve this is to reduce the threshold. However, as the threshold is reduced, the leak current when the gate is OFF increases, the lower limit of the threshold is defined by the acceptable OFF current.
In order to alleviate such a problem, there has been proposed, as a transistor for a low power supply voltage, a dynamic threshold operation transistor which realizes a high driving power at a low voltage by reducing an effective threshold when a transistor is ON (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F. Assaderaghi et al., IEDM94 Ext. Abst. p.809).
FIG. 19
illustrates a simplified structure of such a dynamic threshold operation transistor (hereinafter, referred to as a “DTMOS”). While a NMOS is illustrated, a PMOS can also be realized with symmetrically opposite polarities.
As illustrated in the figure, an SOI substrate
1
is used, and a gate
3
and the substrate
1
are locally short-circuited with an oversized metal line
2
. The essential element is the short-circuiting of the gate
3
and the substrate
1
with each other, and the way they are short-circuited is not limited to the one illustrated.
When a gate bias is applied in the structure in which the gate and the substrate are short-circuited, a forward bias of the same magnitude as the gate bias is applied to a substrate active region. Thus, the same biased state as that in an ordinary translstor results when the gate is OFF. When the gate is ON, the substrate is forwardly biased as the gate bias increases. As a result, the threshold decreases.
However, in this structure, it is necessary, for suppressing the stand-by current, to limit the voltage applied to the gate to about 0.6 V, a voltage at which a lateral parasitic bipolar transistor ts turned ON.
When the gate bias (=body bias) is OPP, such a DTMOS has a leak current comparable to that of an ordinary transistor provided on an SOI substrate and having the same channel state. While the DTMOS is ON, as the gate bias (=body bias) increases, the threshold further decreases, whereby the gate overdrive effect increases, thereby significantly increasing the driving power. The fact that deterioration of mobility is suppressed by the suppression of a vertical electric field on the substrate surface also contributes to the increase in the driving power. Moreover, since the lateral parasitic bipolar transistor is OFF, the significant increase in the stand-by current is suppressed.
However, since the above-described conventional DTMOS uses an SOI substrate, the thickness of the body (the depth of the channel region) is very small (50 nm-200 nm), thereby resulting in a very high resistance. Thus, even if the gate and the body are short-circuited with each other via a contact, a potential is less likely to be transferred to the body at a position farther away from the contact, and the CR time constant increases. Therefore, in view of a transient operation, the effect as a DTMOS is suppressed, and it cannot be operated at a high speed.
Thus, the present invention has been made to solve such problems in the prior art, and has an objective of providing a semiconductor device which realizes a dynamic threshold operation assuming the application of a bulk semiconductor substrate in order to solve the increase in the body resistance of the SOI substrate.
DISCLOSURE OF THE INVENTION
Before the present invention is illustrated, a structure of a semiconductor device based on which the present invention has been made will be discussed.
A semiconductor device based on which the present invention has been made comprises: a semiconductor substrate; a well region of a first conductivity provided on the semiconductor substrate; a source region and a drain region of a second conductivity provided on the well region of the first conductivity type; a channel region provided between the source region and the drain region; a gate insulation film provided on the channel region; and a gate electrode provided on the gate insulation film, wherein the gate electrode is electrically connected to the well region corresponding to the gate electrode.
In such a structure, the resistance of the well region corresponds to the body resistance of the above-described conventional Sol substrate, and the resistance of the well region can be made very small.
More particularly, the body of the above-described conventional SOI substrate has a width equal to the gate length and a length equal to the gate width. Moreover, as described above, the thickness is very thin, i.e., 50 nm-200 nm, and the resistance thereof is very high. For example, when the concentration of the body (i.e., the channel concentration which cannot be high due to the need to reduce the threshold of the transistor) is 1×10
17
/cm
3
, and the thickness of the body is 100 nm, the sheet resistance is then about 10 K&OHgr;. When the gate length is 0-2 &mgr;m, and the gate width is 10 &mgr;m, the aspect ratio is then 50, and the resistance value is 500 K&OHgr;, which is 50 times as great as the sheet resistance.
On the contrary, in the semi conductor device based on which the present invention has been made, the depth of the well region can be set freely.
For example, the width of the well region needs to be at least equal to the total width occupied by the source region, the drain region, and the gate region. In view of the fact that a contact region is provided between the source region and the drain region, it is reasonable to set the width of each of the source region and the drain region to be three times as great as the gate length. Thus, the minimum width of the well region needs to be equal to the sum of the width of the source region, the width of the drain region, and the length of the gate region. Thus, it is reasonable to set the minimum width to be seven times as great as the length of the gate region.
Assuming that the length of the well region is equal to the width of the gate region, the aspect ratio is 1/7.
Moreover, even when the concentration of the well region is the same as that of the body of the SOI substrate, the well region is not limited in the depth direction. Therefore, when the depth is set to 1 &mgr;m to be within a reasonable range, the sheet resistance of the well region is 1/10 of that of the body of the SOI substrate.
In view of the aspect ratio and the sheet resistance, the resistance of the well region can be reduced to about 1/70 of that of the body of the SOI substrate.
Next, a semiconductor device of the present invention which solves the above-described problems based on the semiconductor device having such a structure will be described.
A semiconductor device of claim
1
comprises: a semiconductor substrate; a deep well region of a first conductivity type provided in the semiconductor substrate: a shallow well region
Iwata Hiroshi
Kakimoto Seizou
Matsuoka Toshimasa
Nakano Masayuki
Meier Stephen D.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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