Semiconductor device

Details Semiconductor device Semiconductor device

1999-04-29

2001-07-17

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

C257S674000, C257S690000, C257S678000, C257S779000, C257S784000

Reexamination Certificate

active

06262474

ABSTRACT:

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a semiconductor device that houses semiconductor chips in a casing. More specifically, the present invention relates to a semiconductor device that facilitates electrical connection of the semiconductor chips to the outside via lead-out terminals.
The conventional semiconductor device that houses the semiconductor chips in a casing is electrically connected to the outside via lead-out terminals.
FIG. 9
is a cross sectional view of a conventional semiconductor device. Referring now to
FIG. 9
, a semiconductor device
90
uses a chip
94
of an insulated gate bipolar transistor (IGBT), and the chip
94
is housed in a casing formed of a metal base
91
, a frame
92
and a cover
93
. A substrate
95
made of ceramics, such as alumina and aluminum nitride, is mounted on the metal base
91
. A pattern
95
a
of copper or such a conductive metal is formed on the substrate
95
, and the semiconductor chip
94
is mounted on the copper pattern
95
a
. Patterns
95
b
and
95
c
for terminal connections are formed also on the substrate
95
. The terminal connection patterns
95
b
and
95
c
are connected to the respective electrodes of the semiconductor chip
94
via respective bonding wires
95
d
and
95
e.
A lead-out terminal
96
includes a soldering section
96
a
soldered to the pattern
95
b
, and another lead-out terminal
97
includes a soldering section
97
a
soldered to the pattern
95
c
. An end section
96
b
of the lead-out terminal
96
is fixed to the cover
93
such that a part of the end section
96
b
is exposed to the outside. An end section
97
b
of the lead-out terminal
97
contacts the inner side wall of the frame
92
such that a part of the end section
97
b
is exposed outside the cover
93
or the frame
92
. Alternatively, the end section
96
b
of the lead-out terminal
96
may be fixed to the frame
92
. The end section
97
b
of the lead-out terminal
97
may not contact the inner side wall of the frame
92
.
The semiconductor chip
94
and the lead-out terminals
96
,
97
are sealed with silicone gel
98
filled inside the frame
92
.
The lead-out terminals
96
and
97
are electrically conductive thin plates, and are formed as long as possible, as far as their resistance and inductance are still low sufficiently. The lead-out terminals
96
and
97
are bent perpendicularly to the major faces. Due to these structures, the lead-out terminals
96
and
97
exhibit a capability of relaxing or relieving the stress exerted in an updown or vertical direction in
FIG. 9
from outside, and the stress caused by their own thermal expansion or contraction and exerted in the vertical direction in the figure.
The shapes and arrangements of the terminals in the semiconductor device
90
as shown in
FIG. 9
are determined based on the preliminary structural analysis that employs computer simulation in order to prevent crack formation at the solder. However, when a module assembled based on the results of the computer simulation is subjected to heat cycle tests, cracks are formed sometimes in the solder between the soldering section
96
b
of the lead-out terminal
96
and the pattern
95
b.
This is presumably because the structural analysis by the computer simulation is conducted only in the two dimensions, i.e. in the up-down and right-left directions in
FIG. 9
, and the countermeasures for stress relaxation are taken only in the plane of the figure.
In view of the foregoing, it is an object of the invention to provide a semiconductor device that prevents crack formations in the soldered portions of the lead-out terminals while maintaining the resistance and impedance of the lead-out terminals at low values.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor device that includes a casing; one or more substrates in the casing; one or more semiconductor chips on the one or more substrates; lead-out terminals connecting the one or more semiconductor chips to the outside; and stress relaxing means. Each lead-out terminal includes soldered portions, where the lead-out terminal is soldered to the one or more substrates, and a fixed portion, where the lead-out terminal is fixed to the casing. The stress relaxing means is disposed between the soldered portion and the fixed portion of the lead-out terminal, for relaxing stress along three axes orthogonal to each other.
The stress relaxing means, that relaxes the stress exerted to the lead-out terminal along the orthogonal three axes, prevents crack formations in the soldered portion while suppressing the resistance and the impedance of the lead-out terminal at low values.


REFERENCES:
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patent: 4-32256 (1992-02-01), None
patent: 4-162554 (1992-06-01), None
patent: 5-15444 (1993-02-01), None
patent: 6-268128 (1994-09-01), None

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