Semiconductor device

Details Semiconductor device Semiconductor device

2000-04-13

2001-09-25

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050

Reexamination Certificate

active

06295218

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices, and particularly to a technology effectively applied to a cache memory housed in a data processing device such as a microprocessor and a microcomputer.
Recently, in accordance with an enhancement of a performance of a low-power consumption microprocessor, an enhancement (high-speed and low-power consumption) of a performance of an on-chip cache memory becomes important. In general, methods of comprising a physical address cache may be classified into three methods, i.e., direct map system, full associative system and set associative system. In the recent microprocessor, considering complexity of hardware, hit rate and access time or the like, the set associative system is employed frequently.
With respect to the set associative system, an example of a 2-way set associative system will be described with reference to FIG.
12
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An offset address in the page within a logical address is used to access a cache data array to read two data from the respective ways to the front of the bus. At the same time, a cache tag array is accessed to read out two tags corresponding to the data thus read out and a virtual page number within the logical address is compared with a physical address transformed by a TLB (translation look aside buffer). If the physical address and the tag value agree with each other (hit), then, data of that way is outputted to the bus.
Since a time in which the TLB is accessed and a hit is detected is generally longer than a time required to read out data from the data array, data read out from the data array cannot be outputted to the bus until the hit signal is made definite, thereby resulting in the access time being increased. Further, since two data have to be read out, it is unavoidable that a power consumption increases.
SUMMARY OF THE INVENTION
As a method of solving the above-mentioned problem, there is proposed a method in which a data array is accessed after a way was selected by using a virtual page number. As an example thereof, there is known a circuit (ISSCC Digest of Technical Papers, pp. 174-175, February 1995).
This conventional technology comprises a CAM array (ECAM) having a virtual page number, a CAM array (RCAM) having a physical address and a memory cell array for holding data. When data is read out, one set comprising 8 data (8 ways) is selected by using a page offset address, and further one way is selected by the ECAM. On the basis of the selected result, data is read out by accessing the memory array. At the same time, a value of a corresponding RCAM also is read out and it is checked whether or not the selected way is correct. On the other hand, when data is written, one set is selected, and data is written in the way selected by using the RCAM. That is, this method is a system in which a way is selected in advance by using the logical address and it is verified by using a physical address whether or not the selection is correct.
However, since the RCAM is generally large in bit width and needs a CAM having a bit width at every set, it needs CAM cells of bit width×the number of sets. Accordingly, the existence of the RCAM causes the area to increase and also causes an access time to increase. A general problem encountered with the circuit using the CAM is that, if the data array is not accessed after the way selection (hit determination) by the CAM was completely ended, there is a possibility that erroneous data will be selected. Thus, there are required large timing margins.
That is, in the CAM, a plurality of entries are initially set in the hit state, the comparison is started and other entries are set in the mistake state while leaving one hit entry. After this comparison was ended completely, the hit signal is transmitted to the word driver to activate the word line. If the hit signal had been transmitted to the word driver before the comparison was not ended completely, a plurality of erroneous word lines would be activated. As a result, when the hit signal is transmitted to the word driver after the comparison was ended, there are required large timing margins. Consequently, the access time increases unavoidably.
An outline of representing embodiments disclosed in the present invention will be described in brief as follows:
That is, each way is comprised of a decoder, a word driver, an associative cell array and a memory array. The decoder selects one line by decoding an offset address signal of a logical address. The associative cell array outputs a coincidence signal by comparing a part of virtual page number inputted thereto with data from the associative cell. The word line of the memory array is selected by a logical product of a line selected by the decoder and a way selected by the associative cell array.
In this system, since only one line is activated within one way (WAY), there is then no risk that a plurality of word lines will be simultaneously activated in the same way by mistake. When the word line is activated after the comparison of the associative cell (CAMCELL) was completed, a timing margin is not required. Thus, the access time can be made high in speed as compared with the prior art.
At the same time, it is verified by using a circuit different from the present circuit based on the physical address whether or not the selected way is correct.


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1995 IEEE International Solid-State Circuits Conference,Digest of Technical Papers, pp. 174-175, Feb. 1995.

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