Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-05-23
2001-09-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S618000, C257S623000, C257S692000, C257S786000, C257S620000, C438S068000, C438S113000, C438S460000, C438S462000, C438S620000
Reexamination Certificate
active
06291835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a structure of scribed lines which are formed in a semiconductor substrate and provided for separating chips.
The present application is based on Japanese Patent Application No. Hei. 11-147211, which is incorporated herein by reference.
2. Description of the Related Art
In forming semiconductor devices, a plurality of integrated circuits and the like are generally formed simultaneously on a single semiconductor substrate, and are finally separated along scribed lines. The scribed line is a linear region having a predetermined width where the processing of separation grooves for chip separation is allowed. Conventionally, a number of techniques for forming semiconductor elements and the like for testing, on the scribed lines have been proposed. For example, Japanese Patent Application Laid-Open No. Sho. 57-113241 discloses a technique whereby semiconductor elements for measuring the basic characteristics of circuits or manufacturing parameters are formed on the scribed line or its vicinity so as to make effective use of the scribe regions. For example, Japanese Patent Application Laid-Open No. Sho. 59-14663 discloses a technique whereby areas of monitoring semiconductor elements are made large, and the monitoring semiconductor elements are formed along the scribed lines for the purpose of enhancing the accuracy of detection of faulty withstand pressure ascribable to crystal defects. For example, in Examined Japanese Patent Publication No. Hei. 7-120696, an embodiment shown in
FIG. 2
shows the formation of a monitor pattern on a scribed line to prevent the degree of integration from declining.
However, with the conventionally proposed techniques described above, the portion of the scribed line where the elements are formed and the remaining portion are formed with a fixed uniform width. In order to secure a large effective area for the chip and to reduce the size of the actual chips that are cut out, the width of the scribed lines is preferably narrow. However, if an attempt is made to secure a fixed region for the testing semiconductor element within the scribed line, the reduction of its width is limited by the testing semiconductor element, and therefore there is a limit.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device which permits the reduction of the width of the scribed lines and the reduction of the chip size by making use of a corner portion of a scribed lines in the formation of a semiconductor element therein.
According to the present invention, there is provided a semiconductor device which comprises a semiconductor substrate, a plurality of scribed lines formed on the semiconductor substrate to define a plurality of chips, wherein the chips are separable from each other at the scribed lines, at least one corner portion, at which one of the scribed lines and the other one of the scribed lines are connected, formed to be wider than remaining portions of the scribed lines, and a semiconductor element formed in the corner portion.
In other words, the scribed lines may include first portions having the remaining portions, and second portions wider than the first portions. Accordingly, the corner portion may be defined by at least one of the second portions of the scribed lines and a portion to which one of the scribed lines and the other one of the scribed lines are connected.
In the present invention, the semiconductor element used for a wafer test or the like is formed in the corner portion of the scribed lines having a large width. The semiconductor element may be disposed in a wafer test circuit. In this case, the wafer test circuit is formed in the corner portion. Further, the wafer test- circuit may include test pads. The portion in the vicinity of the corner portion of the scribed lines is a vacant area where bonding pads are generally not located. Accordingly, the enlargement of the width of the corner portion of the scribed lines is possible without increasing the chip size and does not reduce the effective area of the chip. Further, the reduction of the chip size becomes possible by making narrow the width of that portion of the scribed lines which excludes the corner portion and where the semiconductor element is not formed.
It should be noted that the range of groove processing at the time of actual chip separation is limited by the narrow portion of the scribed line, so that the enlargement of the width of the corner portion has no significance in the processing for chip separation. In the present invention, the fact that the width of the corner portion of the scribed lines is enlarged becomes significant in limiting the range where the semiconductor element for testing can be formed.
As described above, in accordance with the present invention, since the corner portion of the scribed lines is made wide and a semiconductor element used for testing or the like is formed therein, it is possible to provide a semiconductor device which permits the reduction of the width of the scribed lines and the reduction- of the chip size.
REFERENCES:
patent: 4835592 (1989-05-01), Zommer
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5285082 (1994-02-01), Axer
patent: 6121677 (2000-09-01), Song et al.
patent: 6174789 (2001-01-01), Tsukada
patent: 6194739 (2001-02-01), Ivanov et al.
patent: 57-113241 (1982-07-01), None
patent: 59-14663 (1984-01-01), None
patent: 2-211649-A (1990-08-01), None
patent: 5-299484-A (1993-11-01), None
patent: 7-120696 (1995-12-01), None
Ito Masahiro
Tsuji Nobuaki
Kang Donghee
Loke Steven
Reed Smith Hazel & Thomas LLP
Yamaha Corporation
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