Semiconductor device

Details Semiconductor device Semiconductor device

1999-11-29

2001-09-25

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230010, C365S201000, C365S189030, C365S230030, C365S239000

Reexamination Certificate

active

06295243

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device as a single-chip implementation of dynamic random access memories (DRAMs) and logic circuits integrated together.
Thanks to recent tremendous increase in the number of, or the density per unit area of, components included within a single semiconductor integrated circuit, a so-called “system LSI”, that is, an LSI with a multiplicity of functional blocks integrated together within a single chip, has become widespread in the art. Among other things, a hybrid LSI, or a single-chip implementation of large-scale logic circuits and DRAMs integrated together, has attracted great attention. A hybrid LSI including a plurality of built-in DRAMs, each performing an equivalent function expected from a conventional general-purpose DRAM, has already been put on the market.
If a number of DRAMs are integrated together on a single chip in this way, then external pins, which have been used as test terminals connected to a general-purpose DRAM, are no longer necessary. That is to say, the number of external terminals applicable to testing each of these DRAMs on a single chip is now limited. Thus, in testing these DRAMs, the number of terminals needed to test each of them should be reduced in some way or other. For example, according to a technique, these DRAMs are serially tested in a time-sharing manner. Alternatively or additionally, the DRAMs are tested while sharing as large a number of external test terminals as possible.
FIG. 13
illustrates an exemplary test scheme applicable to testing each one of DRAMs integrated on a single chip to make up a semiconductor integrated circuit.
Generally speaking, a DRAM usually performs automatic and self-refresh test functions. Thus, the test scheme illustrated in
FIG. 13
is supposed to test a semiconductor integrated circuit with these two test functions.
In this specification, the “auto refresh test function” means refreshing data stored in each memory cell within a DRAM by accessing the memory cell automatically. More specifically, the memory cell is accessed by periodically inputting a rectangular wave through a particular input terminal (i.e., an auto refresh input terminal) and getting a row address generated by an address counter within the DRAM (i.e., a refresh counter) responsive to the input wave.
The “self-refresh test function” also means refreshing data stored in each memory cell within a DRAM by accessing the memory cell. More specifically, the memory cell is accessed responsive to a periodic wave (i.e., a row address sync signal) generated by an oscillator within the DRAM with the level of a self-refresh signal received at a particular input terminal (i.e., a self-refresh input terminal) fixed at the “H” or “L” level.
As shown in
FIG. 13
, a test scheme is provided to test a plurality of semiconductor memory devices
250
A,
250
B, . . . ,
250
X (i.e., DRAMs) included within a conventional semiconductor integrated circuit
200
. Each of these semiconductor memory devices
250
includes a set of nine input terminals
201
,
202
,
203
,
204
,
205
,
206
,
207
,
208
and
209
. Specifically, an inverted row address strobe signal /RAS (i.e., a signal provided to test the operation of the DRAM) is received at the input terminal
201
. An auto refresh test control signal PRAUT is received at the input terminal
202
. A self-refresh test control signal SLF is received at the input terminal
203
. An inverted column address strobe signal /CAS is received at the input terminal
204
. An address ADR is received at the input terminal
205
. An inverted write enable signal /WE is received at the input terminal
206
. An inverted output enable signal /OE is received at the input terminal
207
. A clock signal CLK is received at the input terminal
208
. And a test control signal TEST is received at the input terminal
209
. The test control signal TEST is provided to determine whether a burn-in test or an ordinary DRAM test should be performed.
On the other hand, the chip, or the semiconductor integrated circuit
200
, includes a set of external terminals
211
,
212
,
213
,
214
,
215
,
216
,
217
,
218
and
219
for inputting these signals therethrough. Specifically, the external terminals
211
A,
211
B, . . . ,
211
X are provided for inputting the inverted row address strobe signal /RAS to the individual semiconductor memory devices
250
A through
250
X, respectively. The external terminals
212
A,
212
B, . . . ,
212
X are provided for inputting the auto refresh test control signal PRAUT to the individual semiconductor memory devices
250
A through
250
X, respectively. The external terminal
213
is provided for inputting the self-refresh test control signal SLF in common to all the semiconductor memory devices
250
A through
250
X. The external terminal
214
is provided for inputting the inverted column address strobe signal /CAS in common to all the semiconductor memory devices
250
A through
250
X. The external terminal
215
is provided for inputting the address ADR in common to all the semiconductor memory devices
250
A through
250
X. The external terminal
216
is provided for inputting the inverted write enable signal /WE in common to all the semiconductor memory devices
250
A through
250
X. The external terminal
217
is provided for inputting the inverted output enable signal /OE in common to all the semiconductor memory devices
250
A through
250
X. The external terminal
218
is provided for inputting the clock signal CLK in common to all the semiconductor memory devices
250
A through
250
X. And the external terminal
219
is provided for inputting the test control signal TEST in common to all the semiconductor memory devices
250
A through
250
X.
That is to say, in this arrangement, the total number of external terminals is minimized by connecting the set of input terminals
203
through
209
in each of the semiconductor memory devices
250
A through
250
X to the respective common external terminals
213
through
219
.
In addition, each of these semiconductor memory devices
250
A through
250
X includes a test data (TDQ) input/output terminal
221
.
On the output end of the semiconductor integrated circuit
200
, the test data input/output terminals
221
of all the semiconductor memory devices
250
A through
250
X are connected in common to a single set of external terminals
231
through an input/output bus
241
.
On the input end of the semiconductor integrated circuit
200
provided with such a test scheme, when the inverted row address strobe signal /RAS is asserted (e.g., falls to the “L” level), an associated DRAM is activated. When the signal /RAS is negated (e.g., rises to the “H” level), the associated DRAM enters a standby mode. Accordingly, if the DRAMs are serially tested one by one in a time-sharing fashion, then the number of terminals needed for testing can be cut down by taking advantage of this function. That is to say, as shown in
FIG. 13
, the dedicated inverted row address strobe signal external terminals
211
A through
211
X are provided for the DRAMs
250
A through
250
X, respectively. And a test is carried out by asserting only the inverted row address strobe signal /RAS associated with the DRAM under test while negating the inverted row address strobe signals /RAS associated with the other DRAMs. In such a case, the external terminals
213
through
219
for inputting the signals other than the inverted row address strobe signal /RAS and the auto refresh test control signal PRAUT can be shared among all the semiconductor memory devices
250
A through
250
X.
Also, when the inverted row address strobe signal /RAS is negated, the associated DRAM comes to have a high impedance HIZ. Thus, on the output end of the semiconductor integrated circuit
200
, only a DRAM associated with an asserted inverted row address strobe signal /RAS is accessed through the test data input/output bus
241
. Accordingly, the external terminal
231
for the test data input/output bus
241
can also be used in common

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