Semiconductor device

Details Semiconductor device Semiconductor device

2000-02-10

2001-09-11

Clark, Jhihan B (Department: 2815)

Compositions

Liquid crystal compositions

C257S203000, C257S208000

Reexamination Certificate

active

06287482

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a master structure and a layout constitution of a gate array (GA) and an embedded array (EA).
2. Related Background Art
In recent years, with the popularization of portable electronic apparatuses such as notebook type computers, it has often been intended to reduce a packaging area by integrating peripheral circuits of CPU into one chip. Such a multifunctional chip is generally constituted using a gate array or an embedded array.
FIG. 1
is a layout diagram of a conventional gate array. The conventional gate array has an internal cell area
1
on which various logic circuits are formed, a pad area
2
connected to external wirings, and an I/O cell area
3
formed between the internal cell area
1
and the pad area
2
. Each input/output terminal in the internal cell area
1
is connected to the corresponding pad in the pad area
2
through the I/O cell area
3
.
In the pad area
2
, a plurality of pads are formed at predetermined intervals. Each pad is connected to a corresponding external pin of a package (not shown) via a carrier tape (not shown).
The above-described multifunctional chip communicates with many kinds of external signals, and hence, a number of pads for external connection have to be disposed in the chip. In the conventional gate array, however, the pad area
2
is formed only on the outside periphery of the chip as shown in
FIG. 1
, so that the number of the pads cannot sufficiently be increased. Therefore, even when an empty space is present in the internal cell area
1
or the I/O cell area
3
, there is a problem that the circuit cannot be formed because of the shortage of the pad area
2
.
SUMMARY OF THE INVENTION
The present invention has been developed in consideration of the above-mentioned problem, and an object thereof is to provide a semiconductor device on which it is possible to form a number of pads for external connection.
To attain the above-described object, according to the present invention, there is provided a semiconductor device comprising:
an internal cell area on which various logic circuits can be formed;
a pad area on which a plurality of pads for connection to the outside are formed; and
an I/O cell area for receiving/transmitting signals between the internal cell area and the pad area;
the pad area including:
an external pad area formed outside the I/O cell area; and
an internal pad area formed between the internal cell area and the I/O cell area.
According to another aspect of the present invention, there is provided a semiconductor device comprising:
an internal cell area on which various logic circuits can be formed;
a pad area on which a plurality of pads for connection to the outside are formed; and
an I/O cell area for receiving/transmitting signals between the internal cell area and the pad area;
the pad area including:
an external pad area formed outside the I/O cell area; and
an internal pad area formed along an outer edge of the internal cell area and inside the internal cell area.
According to the present invention, since not only the pad area is disposed outside the I/O cell area, but also the internal pad area is disposed between the I/O cell area and the internal cell area, resulting in increase of the number of pins. Moreover, since a pad interval does not need to be narrowed, reliability is improved, and manufacture yield is raised.
Furthermore, since a wiring layer for connecting the internal pad area and the I/O cell area can be formed on the same layer (e.g., a third layer) as a wiring layer in the internal cell area, a new wiring layer for the internal pad area does not need to be disposed, resulting in simplification of a manufacture process.


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