Semiconductor device

Details Semiconductor device Semiconductor device

1993-05-20

1996-02-06

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257376, 257463, H01L 2968

Patent

active

054897947

ABSTRACT:
The semiconductor device contains a CMOS transistor pair comprised of a P channel MOS transistor having a polysilicon gate 4 and an N channel MOS transistor having a polysilicon gate. The MOS transistor has a channel dope layer 5 localized in a vicinity of a surface of a channel region just below a gate electrode. This channel dope layer 5 has a quite shallow p-n junction depth xj effective to suppress a leak current. Thereby, an amount of impurity concentration in the surface of the channel region can be reduced to improve a subthreshold characteristics of the MOS transistor and to enable a low voltage and high speed operation under suppressing a leakage current.

REFERENCES:
patent: 4799092 (1989-01-01), Klaassen
International Electron Devices Meeting, Dec. 5, 1983, Washington, D.C., pp. 534-537, Shang-yi Chiang et al., "Optimization of sub-micron P-channel FET structure".
Patent Abstracts Of Japan, vol. 011, No. 254 (E533), Aug. 18, 1987.
1989 Symposium on VLSI Technology Digest of Technical Papers, May 22, 1989 Kyoto, Japan, pp. 13-14, Y. Okazaki et al., "A High Performance 0.22 um Gate CMOS Technology".
Extended Abstracts, vol. 87, No. 1, 1987 (Spring), Princeton, N.J., p. 211, Y. Nishi, "CMOS Technology Status and Challenges".

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