Semiconductor device

Details Semiconductor device Semiconductor device

1997-02-04

1999-05-18

Meier, Steohen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

H01L27/01;27/12;31/0392

Patent

active

059052864

ABSTRACT:
In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

REFERENCES:
patent: 4753896 (1988-06-01), Matloubian
patent: 5023197 (1991-06-01), Haond et al.
patent: 5039621 (1991-08-01), Pollack
patent: 5294281 (1994-03-01), Iwamaysu
patent: 5550397 (1996-08-01), Lifshitz et al.
Electronics Letters, Aug. 18, 1983, vol. 19 No. 17, pp. 684-685.
"Novel LSI/SOI Wafer Fabrication Using Device Layer Transfer Technique", Hamaguchi et al., IEDM 85, pp. 688-691.

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