Semiconductor device

Details Semiconductor device Semiconductor device

1998-08-25

2000-11-28

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257676, 257691, H01L 23495

Patent

active

061539228

ABSTRACT:
In a package having an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

REFERENCES:
patent: 5068712 (1991-11-01), Murakami et al.
patent: 5532189 (1996-07-01), Kiyono
patent: 5559366 (1996-09-01), Fogal et al.
patent: 5576246 (1996-11-01), Conru et al.
patent: 5796158 (1998-08-01), King
patent: 5834831 (1998-11-01), Kubota et al.

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