Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257390, 257401, 365214, H01L 2710, H01L 2715

Patent

active

054689856

ABSTRACT:
There is provided a semiconductor device having a wiring configuration which can suppress an increase in the delay time of a wiring extending over the memory cell area even if the cell size is reduced. Wirings of preset wiring length are formed over a semiconductor substrate. A wiring of wiring length larger than that of the former wirings is formed over the former wirings with an inter-level insulation film disposed therebetween and the width of the latter wiring is made large. Thus, the wiring resistance is reduced and the wiring delay time can be effectively reduced. The semiconductor device is applied to a semiconductor memory or the like in which cell selection is made by use of the hierarchical structure such as a duplex word line system.

REFERENCES:
patent: 4782465 (1988-11-01), Uchida
patent: 5172335 (1992-12-01), Sasaki et al.
patent: 5241495 (1993-08-01), Sasaki

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