Semiconductor device

Details Semiconductor device Semiconductor device

2008-01-08

2011-11-15

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000

Reexamination Certificate

active

08058682

ABSTRACT:
A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.

REFERENCES:
patent: 5216275 (1993-06-01), Chen
patent: 5282018 (1994-01-01), Hiraki et al.
patent: 5637898 (1997-06-01), Baliga
patent: 5767548 (1998-06-01), Wondrak et al.
patent: 5864159 (1999-01-01), Takahashi
patent: 5973359 (1999-10-01), Kobayashi
patent: 5998833 (1999-12-01), Baliga
patent: 6040600 (2000-03-01), Uenishi et al.
patent: 6069372 (2000-05-01), Uenishi
patent: 6078090 (2000-06-01), Williams et al.
patent: 6114727 (2000-09-01), Ogura et al.
patent: 6184555 (2001-02-01), Tihany et al.
patent: 6191447 (2001-02-01), Baliga
patent: 6201291 (2001-03-01), Kordic et al.
patent: 6251730 (2001-06-01), Luo
patent: 6388286 (2002-05-01), Baliga
patent: 6509233 (2003-01-01), Chang et al.
patent: 6525373 (2003-02-01), Kim
patent: 6541820 (2003-04-01), Bol
patent: 6608350 (2003-08-01), Kinzer et al.
patent: 6649975 (2003-11-01), Baliga
patent: 6677641 (2004-01-01), Kocon
patent: 6686244 (2004-02-01), Blanchard
patent: 6710403 (2004-03-01), Sapp
patent: 6724042 (2004-04-01), Onishi et al.
patent: 6803627 (2004-10-01), Pfirsch
patent: 6812525 (2004-11-01), Bul et al.
patent: 7230310 (2007-06-01), Chen
patent: 2001/0041407 (2001-11-01), Brown
patent: 2003/0071616 (2003-04-01), Hauenstein
patent: 2003/0203576 (2003-10-01), Kitada et al.
patent: 2004/0150040 (2004-08-01), Nitta et al.
patent: 2005/0032291 (2005-02-01), Baliga
patent: 2006/0060916 (2006-03-01), Girdhar et al.
patent: 2006/0118853 (2006-06-01), Takata et al.
patent: 2006/0214222 (2006-09-01), Challa et al.
patent: 2006/0267090 (2006-11-01), Sapp et al.
patent: 2007/0158740 (2007-07-01), Yoshikawa et al.
patent: 0325161 (1989-07-01), None
patent: 1583152 (2005-10-01), None
Grant et al.,Power MOSFETS Theory and Applications, John Wiley & Sons Ltd., 1989, p. 68-74.
Kazerounian et al., “CODMOS—A Depletion MOSFET Using Fixed Oxide Charge”, 41st Annual Device Research Conference, IEEE Electron Devices Society, Jun. 20-22, 1983.
Konig et al., “The Negatively Charged Insulator-Semiconductor Structure: Concepts, Technological Considerations and Applications,”. Solid State Electronics, 2000; 44(1): 111-116.
Pfiester et al., “Gain-enhanced LDD NMOS Device Using Cesium Implantation,” IEEE Transactions on Electron Devices, Jun. 1992; 39(6): 1469-1476.
Watt et al., “A Low-Temperature NMOS Technology with Cesium-Implanted Load Devices” IEEE Trans. Electron Devices, 34, Jan. 1987, pp. 28-38.
International Search Report and Written Opinion of PCT Application No. PCT/US08/50505, dated Jul. 7, 2008, 17 pages total.
J. T. Watt, B. J. Fishbein & J. D. Plummer; Low-Temperature NMOS Technology with Cesium-Implanted Load Devices; IEEE Trans.Electron Devices, vol. 34, # 1, Jan.'87; p. 28-38.
J.T.Watt,B.J.Fishbein & J.D.Plummer;Characterization of Surface Mobility in MOS Structures Containing Interfacial Cesium Ions;IEEE Trans.Electron Devices,V36,Jan.'89; p. 96-100.
J.R.Pfiester, J.R.Alvis & C.D.Gunderson; Gain-Enhanced LDD NMOS Device Using Cesium Implantation; IEEE Trans.Electron Devices, V39, #6, Jun.'92; p. 1469-1476.
International Search Report and Written Opinion mailed Jul. 2, 2008 for PCT/US 08/50532 filed Jan. 8, 2008.

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