Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S280000, C257SE29242

Reexamination Certificate

active

07732868

ABSTRACT:
A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.

REFERENCES:
patent: 4261004 (1981-04-01), Masuhara et al.
patent: 4339285 (1982-07-01), Pankove
patent: 4387386 (1983-06-01), Garver
patent: 4626802 (1986-12-01), Gailus
patent: 4745445 (1988-05-01), Mun et al.
patent: 4803527 (1989-02-01), Hatta et al.
patent: 4843440 (1989-06-01), Huang
patent: 4965863 (1990-10-01), Cray
patent: 5047355 (1991-09-01), Huber et al.
patent: 5157573 (1992-10-01), Lee et al.
patent: 5371405 (1994-12-01), Kagawa
patent: 5374899 (1994-12-01), Griffiths et al.
patent: 5559363 (1996-09-01), Immorlica, Jr.
patent: 5654860 (1997-08-01), Casper et al.
patent: 5684323 (1997-11-01), Tohyama
patent: 5821827 (1998-10-01), Mohwinkel et al.
patent: 5841184 (1998-11-01), Li
patent: 5932917 (1999-08-01), Miura et al.
patent: 5986863 (1999-11-01), Oh
patent: 6002860 (1999-12-01), Voinigescu et al.
patent: 6265756 (2001-07-01), Brockett et al.
patent: 6580107 (2003-06-01), Higashino et al.
patent: 6914280 (2005-07-01), Asano et al.
patent: 6946891 (2005-09-01), Asano et al.
patent: 7193255 (2007-03-01), Asano
patent: 2002/0024375 (2002-02-01), Asano et al.
patent: 2002/0047177 (2002-04-01), Asano et al.
patent: 2004/0077150 (2004-04-01), Tosaka
patent: 2004/0130380 (2004-07-01), Asano et al.
patent: 2004/0222469 (2004-11-01), Asano et al.
patent: 2004/0223274 (2004-11-01), Asano et al.
patent: 2005/0121730 (2005-06-01), Asano et al.
patent: 2005/0263796 (2005-12-01), Asano
patent: 2005/0274979 (2005-12-01), Asano
patent: 2005/0277255 (2005-12-01), Asano
patent: 2005/0285143 (2005-12-01), Asano
patent: 2006/0163609 (2006-07-01), Asano et al.
patent: 2006/0163659 (2006-07-01), Asano et al.
patent: 2006/0164150 (2006-07-01), Asano
patent: 2006/0252651 (2006-11-01), Asano et al.
patent: 2006/0255403 (2006-11-01), Asano et al.
patent: 2006/0289963 (2006-12-01), Asano et al.
patent: 1492585 (2004-04-01), None
patent: 3334167 (1985-04-01), None
patent: 0140095 (1985-05-01), None
patent: 0 700 161 (1996-03-01), None
patent: 57-128983 (1982-08-01), None
patent: 60-86874 (1985-05-01), None
patent: 62-174975 (1987-07-01), None
patent: 2-162744 (1990-06-01), None
patent: 8-236549 (1996-09-01), None
patent: 2723936 (1997-11-01), None
patent: 11-220093 (1999-08-01), None
patent: 2002-368194 (2002-12-01), None
patent: 2004-103786 (2004-04-01), None
patent: 1998-043416 (1998-09-01), None
patent: 1998-065222 (1998-10-01), None
patent: 2002-93613 (2002-12-01), None
patent: WO-96/22613 (1996-07-01), None
patent: WO-97/45877 (1997-04-01), None
patent: WO-97/45877 (1997-12-01), None
Miyawaki, Yasuo et al. (1986) “Ion-Implanted Low Noise Dual-Gate GaAs MESFET,” Sanyo Technical Review 18(2), pp. 76-84.
Physics of Semiconductor Devices, pp. 116-123.
Anderson, W.R. et al. “ESD Protection under Wire Bonding Pads,” EOS/ESD Symposium, Jan. 1, 1999, pp. 88-94.
European Search Report dated Dec. 3, 2008 directed towards foreign application No. 02788677.9; 4 pages.
European Office Action directed towards a counterpart EP application No. 02788677.9 mailed Mar. 5, 2009; (5 pages).
European Search Report dated Jul. 6, 2009 directed towards related foreign application EP03794280.2; (3 pages).
European Search Report mailed Sep. 21, 2009, directed to EP Patent Application No. 03 794 280.2; 6 pages.
Asano, T., U.S. Office Action mailed on Feb. 5, 2009, directed to a related U.S. Appl. No. 11/314,101; 7 pages.
Asano, T., U.S. Office Action mailed on Jun. 11, 2008, directed to a related U.S. Appl. No. 11/314,101; 9 pages.
Asano, T., U.S. Office Action mailed on Jan. 25, 2006, directed to a related U.S. Appl. No. 10/772,585; 7 pages.
Asano, T., U.S. Office Action mailed on Sep. 6, 2006, directed to a related U.S. Appl. No. 10/772,585; 7 pages.
Asano, T., U.S. Office Action mailed on Sep. 18, 2006 directed to a related U.S. Appl. No. 10/505,438; 15 pages.
Asano, T., U.S. Office Action mailed on Mar. 2, 2006, directed to a related U.S. Appl. No. 10/505,438; 13 pages.
Asano, T., U.S. Office Action mailed on Jan. 6, 2009, directed to a related U.S. Appl. No. 11/314,178; 11 pages.
Asano, T., U.S. Office Action mailed on Jul. 17, 2008, directed to a related U.S. Appl. No. 11/314,178; 13 pages.

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