Semiconductor device

Static information storage and retrieval – Systems using particular element – Amorphous

Reexamination Certificate

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C365S148000

Reexamination Certificate

active

07830706

ABSTRACT:
A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

REFERENCES:
patent: 7394680 (2008-07-01), Toda et al.
patent: 7606059 (2009-10-01), Toda
patent: 2004/0232460 (2004-11-01), Kajiyama
patent: 2005/0169037 (2005-08-01), Nishihara
patent: 2009/0141532 (2009-06-01), Nagashima et al.
patent: 2010/0058127 (2010-03-01), Terao et al.
patent: 2003-060171 (2003-02-01), None
patent: 2004-266220 (2004-09-01), None
patent: 2007-501519 (2007-01-01), None
patent: WO 2005/017904 (2005-02-01), None
Kwang-Jin Lee et al., “A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput”, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, USA, 2007, pp. 472-473 and 616.

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