Semiconductor device

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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Details

C365S230050, C365S203000, C365S233100

Reexamination Certificate

active

07742350

ABSTRACT:
A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value.

REFERENCES:
patent: 7505339 (2009-03-01), Ohbayashi
patent: 2006134379 (2006-05-01), None

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