Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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Details

C257S700000, C257S758000, C257S773000, C257S775000, C257S784000

Reexamination Certificate

active

07741724

ABSTRACT:
This invention is directed to offer a semiconductor device having a structure capable of relaxing a mechanical stress applied to a bonding pad. A third interlayer insulation film having via holes is formed on a second interlayer insulation film to cover a third wiring layer. A third conductive layer is formed in the via hole. The third interlayer insulation film is composed of an array of a plurality of hexagonal column-shaped interlayer insulation films. And the via hole and the third conductive layer are formed to surround each hexagonal column-shaped interlayer insulation film. A fourth wiring layer connected with the third wiring layer through the third conductive layer is formed. The fourth wiring layer makes an uppermost wiring layer in an embodiment of this invention and serves as the bonding pad.

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patent: 6143396 (2000-11-01), Saran et al.
patent: 7312530 (2007-12-01), Hashimoto et al.
patent: 7420280 (2008-09-01), Kelkar
patent: 2002/0017672 (2002-02-01), Ker et al.
patent: 2002/0195723 (2002-12-01), Collette
patent: 2005/0067707 (2005-03-01), Hashimoto et al.
patent: 05-343466 (1993-12-01), None
patent: 06-196525 (1994-07-01), None
patent: 06-283682 (1994-10-01), None
patent: 09-312332 (1997-12-01), None
patent: 2002-110731 (2002-04-01), None
patent: 2005-123587 (2005-05-01), None

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