Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2007-07-18
2010-11-23
Zarneke, David A (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE23145
Reexamination Certificate
active
07838996
ABSTRACT:
A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.
REFERENCES:
patent: 7112858 (2006-09-01), Inaba et al.
patent: 2006/0118963 (2006-06-01), Yamada
patent: 2006/0194429 (2006-08-01), Hashimoto et al.
patent: 2006/0234165 (2006-10-01), Kamigaki et al.
patent: 07-263677 (1995-10-01), None
patent: 2006-156657 (2006-06-01), None
U.S. Appl. No. 11/826,224, filed Jul. 13, 2007, to Kito.
Kito Masaru
Nagata Yuzo
Sato Mitsuru
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Wagner Jenny L
Zarneke David A
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