Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-07-10
2007-07-10
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
11206170
ABSTRACT:
An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.
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Eto Satoshi
Kawamura Noriko
Miyo Toshiya
Nakamura Toshikazu
Sato Ayako
Chesser Wilburn L.
Fujitsu Limited
Haydoutova Juliana
Kerveros James C
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