Semiconductor device

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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Details

C365S154000

Reexamination Certificate

active

07009862

ABSTRACT:
Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

REFERENCES:
patent: 4646271 (1987-02-01), Uchiyama et al.
patent: 4780845 (1988-10-01), Threewitt
patent: 5490102 (1996-02-01), Jubran
patent: 5495382 (1996-02-01), Albon
patent: 6154384 (2000-11-01), Nataraj et al.
patent: 6584003 (2003-06-01), Kim et al.
patent: 2004/0012040 (2004-01-01), Osada et al.
patent: 2004/0114411 (2004-06-01), Node et al.
patent: 2001-28401 (2001-01-01), None

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