Semiconductor device

Details Semiconductor device Semiconductor device

2006-08-22

2006-08-22

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

C257S791000, C257S792000, C257S793000, C257S794000, C257S750000

Reexamination Certificate

active

07095124

ABSTRACT:
A semiconductor device comprises a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate and a sealing resin layer which coats the semiconductor chip. The sealing resin layer meets, in coefficient of linear expansion (α) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1)in-line-formulae description="In-line Formulae" end="lead"?E<0.891/{(α−αs)2×h}  (1)in-line-formulae description="In-line Formulae" end="tail"?whereE represents the Young's modulus (GPa) of the sealing resin at room temperature;α represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature;αs represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; andh represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.

REFERENCES:
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patent: 6166433 (2000-12-01), Takashima et al.
patent: 6265784 (2001-07-01), Kawano et al.
patent: 6448665 (2002-09-01), Nakazawa et al.
patent: 6512176 (2003-01-01), Yaguchi et al.
patent: 6847125 (2005-01-01), Tanaka et al.
patent: 9-246464 (1997-09-01), None
patent: 10-321769 (1998-12-01), None
patent: 2000-11424 (2000-04-01), None
patent: 2002-141436 (2002-05-01), None
Notification of Reasons for Rejection (Japanese Office Action), Oct. 25, 2005, for Japanese Patent Application No. 2003-369286.

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