Semiconductor device

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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C365S189050

Reexamination Certificate

active

07038961

ABSTRACT:
A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.

REFERENCES:
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patent: 6385100 (2002-05-01), Noda et al.
patent: 6480415 (2002-11-01), Makuta et al.
patent: 6538933 (2003-03-01), Akioka et al.
Manzur Gill, Tyler Lowrey and John Park, “Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications”, 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 3 pages.
A. Pirovano, A.L. Lacaita, D. Merlani, A. Benvenuti, F. Pellizzer and R. Bez, “Electronic Switching Effect in Phase-Change Memory Cells”, 2002 IEEE International Electron Devices Meeting, Technical Digest, pp. 923-926.
Y.N. Hwang et al., “Completely CMOS-Compatible Phase-Change Nonvolatile RAM Using NMOS Cell Transistors”, 2003 Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, pp. 91-92.

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