Semiconductor device

Electronic digital logic circuitry – Tri-state

Reexamination Certificate

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Details

C326S057000, C326S058000, C326S082000

Reexamination Certificate

active

07049847

ABSTRACT:
A semiconductor device including a tristate buffer circuit, which includes, on an output stage, at least a first transistor (P1) for pull-up driving and a second transistor (N1) for pull-down driving, in which, when a control signal (EN) is of a value indicating an enable state, an output is set to a high level or to a low level, depending on a data signal, and in which, when the control signal is of a value indicating a disable state, the first and second transistors are turned off to set a high impedance state of the output. The semiconductor device further includes a control unit (120, P6, P7) for performing control for speeding up the transition from the on-state to the off-state of the first transistor (P1) at the time of switching the control signal (EN) from the enable state to the disable state.

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patent: 5933025 (1999-08-01), Nance et al.
patent: 6731134 (2004-05-01), Bucossi et al.
patent: 2002/0145445 (2002-10-01), Iizuka
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Japanese Offices Action dated Aug. 30, 2005 (with partial English translation).

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