Semiconductor device

Details Semiconductor device Semiconductor device

2005-11-01

2005-11-01

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06961881

ABSTRACT:
A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

REFERENCES:
patent: 5682352 (1997-10-01), Wong et al.
patent: 6505317 (2003-01-01), Smith et al.

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