Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S786000, C257S784000, C257S738000, C257S774000, C257S778000, C174S050510

Reexamination Certificate

active

06838767

ABSTRACT:
Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.

REFERENCES:
patent: 4935637 (1990-06-01), Kaifu et al.
patent: 6054755 (2000-04-01), Takamichi et al.
patent: 6060775 (2000-05-01), Ano
patent: 6064111 (2000-05-01), Sota et al.
patent: 6160313 (2000-12-01), Takashima et al.
patent: 6198165 (2001-03-01), Yamaji et al.
patent: 6232650 (2001-05-01), Fujisawa et al.
patent: 6232661 (2001-05-01), Amagai et al.
patent: 6242815 (2001-06-01), Hsu et al.
patent: 9-121002 (1997-05-01), None
patent: 11-204549 (1999-07-01), None
“Electronic Parts and Materials”, Sep. 1998, published by Kogyo Chosakai, pp. 22-52.

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