Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2000-01-28
2004-08-10
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S690000, C257S692000, C257S735000, C257S738000
Reexamination Certificate
active
06774466
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, particularly, to a semiconductor package having a structure which is adequate for decreasing the electrical resistance of the semiconductor package without a Si chip.
An example of a conventional transistor package is disclosed in JP-A-8-64634 (1994). A semiconductor chip, whereon electronic circuits are formed, is bonded to a die pad for heat release at a rear plane electrode side by welding. A bump is formed on an Al electrode at a circuit formed plane side of the chip, and an inner lead is connected electrically and mechanically thereon. An inner lead is also connected to the die pad, and the chip, the die pad, and a part of the lead is sealed with resin so as to cover them. In a case when the bump is solder, the lead side is plated with tin (Sn), gold (Au), or solder, and the like, and bonded with the bump by melting the solder of the bump. In a case when the bump is gold, the lead is plated with tin, and bonded with the bump by an Au—Sn eutectic reaction. The inner lead is composed of three lines provided for a source electrode, a drain electrode, and a gate electrode, respectively. The lead for the source electrode is manufactured in a comb teeth shape. A through opening to the resin is formed on the head.JP-A-5-121615 (1993) discloses a surface mounting type semiconductor package having a wireless structure as another conventional example. Three external connection terminals are connected to electrode terminals of the semiconductor chip. Two electrodes on an upper surface of the chip are connected to the external connection terminals by thermocompression bonding of Au balls. Mounting on a circuit substrate is performed by soldering the tip region of the lead terminals, which protrude forward and backward from the chip mounting portion, to the terminals of the substrate.
In accordance with a conventional standard surface mounting type semiconductor package, the semiconductor chip is bonded to the die pad of the lead for the drain by soldering, and the source electrode and the gate electrode of the semiconductor chip are connected to the leads for the source and the gate of the external connection terminals by Al wire bonding. The chip, each respective lead, and a part of the die pad are molded with resin. The die pad is exposed at the bottom of the resin body so as to allow the structure of the resin body to be connected to the circuit substrate, and its size is set to be larger than the size of the resin mold.
In accordance with the conventional chip die pad bonding structure of a semiconductor chip, a bonding structure using a resin with conductive particles, wherein Pb rich solder having a low yield strength or Ag particles are mixed, has been adopted in order to prevent the chip from generating a high stress when the chip is fixed to a member made of a Cu base alloy.
The electrical resistance of the semiconductor package without a Si chip in the surface mounting type plastic package of a conventional vertical semiconductor element has been from several tens m&OHgr; to ten and several m&OHgr; with a wire bonding structure. In accordance with advancement of semiconductor technology, the on-resistance of the element has been decreasing year by year, and at present, a device of several tens to several m&OHgr;/cm
2
has been developed. Further decrease of the resistance can be expected in future. In that case, a decrease of the electrical resistance of the semiconductor package without a Si chip is indispensable for improving the performance of the semiconductor package, because the electrical resistance of a semiconductor package without a Si chip becomes larger than the device resistance. A prior technique regarding the on-resistance of the semiconductor package is disclosed in JP-A-8-64634. The prior proposed technique relates to an insert mounting type package. The insert mounting type package is not restricted in size, and a thick and large size die pad can be used, because the bonding between the substrate and the lead is strong structurally. Therefore, a decrease of the electrical resistance of the semiconductor package without a Si chip is relatively easy. However, the surface mounting type package has a property that the fatigue strength of the bonding portion is weaker than that of the insert mounting type package, because it has a structure in which the tip of the leads protruding from both sides of the resin body are bonded to the terminal of the substrate by soldering two planes of small area to each other. Therefore, it is necessary to absorb the thermal strain between the package and the substrate resulting from heat generation of the chip which causes deformation of the flexible leads. Accordingly, it is necessary to make the shape of the leads thin and slender. In this case, a decrease of the electrical resistance of the semiconductor package without a Si chip is difficult, because the electrical resistance of the lead itself is large.
In the case of a surface mounting type package, the above problem can be solved by adopting a structure wherein the die pad mounting the chip is soldered directly to the circuit substrate. However, if a position where the lead, to be connected to the electrode at an upper surface of the chip, protrudes from the resin body differs in height from the position where the die pad protrudes, the contacting planes of the upper and lower metal molds for molding the resin form a three dimensional structure, such that a problem is created in that the manufacture of the metal molds becomes difficult. The above problem becomes significant when the lead frame is a matrix frame (arranged in X and Y directions) and the objective is to manufacture a large number of the packages, simultaneously. The problem can be solved by making the size of the die pad to be contained in the resin body small, but if so, a pressing portion to press the die pad onto the bottom surface of the metal mold must be provided in the metal mold, in order to expose the die pad at the lower plane of the resin body. If the size of the die pad is sufficiently large, it is possible to press the die pad onto the bottom surface of the metal mold. However, if the size of the die pad is the same as the size of the chip, the pressing portion can not be found on the die pad, and a problem is created in that the die pad is molded while being exposed at the bottom of the resin body. Therefore, in case of a small size semiconductor package, wherein the size of the die pad is the same as the size of the chip, it is difficult to assembly the structure in such a manner that the die pad concurrently operating as the external connection terminals of the rear electrode is contained in the resin body.
On the other hand, conventionally, a soldering connection or an adhering structure with a resin using conductive particles has been adopted for the connection of the rear plane of the chip with the external connection terminals, such as a die pad, and others. The soldering connection is a superior connection with regard electrical resistance, thermal resistance, and heat resistance reliability. However, currently, in view of environmental problems, no use of Pb is employed, and the conventional soldering material containing Pb must be replaced with a new bonding material containing no Pb. There are various soldering materials containing no Pb having a solidus line temperature below 250° C., but actually, there is no adequate soldering material containing no Pb having a solidus line temperature higher than 270° C., which is durable against severe mounting on the substrate of the package. The only exception is Au—Si solder having a solidus line temperature of 370° C. However, Au—Si solder can not be adopted as the soldering material for the electrode at the rear plane of the chip, for two reasons, such as high cost and generation of cracks in the chip during the cooling step after soldering when the size of the chip is large, because of the high yield strength. Therefore, a problem exists in that there is
Hata Toshiyuki
Hirashima Toshinori
Ishii Shigeru
Kajiwara Ryoichi
Kishimoto Munehisa
Antonelli Terry Stout & Kraus LLP
Chambliss Alonzo
Renesas Technology Corp.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342964