Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-11-27
2004-06-29
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
Reexamination Certificate
active
06756816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device technology. The term semiconductor device includes a liquid crystal display device using a liquid crystal element for a pixel, and a display device using an electroluminescence (EL) element or other light emitting element. It also includes circuits or the like for inputting video signals to pixels arranged in the above display devices to display images. It also includes a shift register circuit, a latch circuit, a buffer circuit, a pulse output circuit such as a level shifter circuit, and an amplifying circuit such as an amplifier.
2. Description of the Related Art
Semiconductor devices in which a semiconductor thin film is formed on an insulator such as a glass substrate, especially liquid crystal display devices using thin film transistors (hereinafter referred to as TFTs) and other active matrix display devices, have been utilized in many products and propagated in recent years. Active matrix display devices display images by controlling the luminance of each of ten thousands to millions of pixels that are arranged to form a matrix pattern using a TFT that is placed in each pixel.
A technique of forming a pixel portion and peripheral circuits integrally on the same substrate using polysilicon TFTs is being advanced. The technique is of a great help in reducing devices in size and lowering the power consumption, and accordingly is used in display units and the like of portable information terminals where application fields of the technique are expanding at remarkable rate.
An example of forming a pixel portion and peripheral circuits on the same substrate using polysilicon TFTs is described with reference to FIG.
10
.
FIG. 10
shows a source signal line driving circuit as an example of a semiconductor device used in a typical display device, and a description is given below on its structure and operation.
In
FIG. 10
, the source signal line driving circuit has a shift register
1000
composed of plural stages of pulse output circuits
1001
for sequentially outputting sampling pulses in response to clock signals (S-CK), inverted clock signals (S-CKB), and start pulses (SP). The driving circuit also has a first latch circuit
1002
for holding 3-bit digital video signals (DATA
1
to
3
) in response to input of the sampling pulses, and a second latch circuit
1003
for holding digital video signals in response to input of latch pulses. Furthermore, the driving circuit has a D/A converter
1004
for converting a digital video signal into an analog video signal.
Though not shown in the drawing, the driving circuit may have a buffer. The bit number of digital video signals is not limited to 3.
Next, a brief description is given below on the operation of the source signal line driving circuit. The shift register
1000
sequentially outputs sampling pulses in response to input of clock signals (S-CK), inverted clock signals (S-CKB), and start pulses (SP). The first latch circuit
1002
holds digital video signals (DATA
1
to
3
) in response to input of the sampling pulses. Holding of a digital video signal is timed to coincide with input of a sampling pulse. After this operation is finished for one horizontal period, latch pulses are inputted during a horizontal retrace period and the digital video signals for one horizontal period which have been held in the first latch circuit
1002
are transferred to the second latch circuit
1003
at once. Thereafter, the digital video signals are inputted to the D/A converter circuit
1004
and converted into voltage signals for the respective gray scales, and the voltage signals are written in source signal lines (S
0001
to the last S).
In the semiconductor device described above, a CMOS circuit obtained by combining an n-channel TFT and a p-channel TFT is often used. However, forming a CMOS circuit that is a combination of an n-channel TFT and a p-channel TFT on one insulating surface means forming TFTs that have opposing conductivity types on the same insulating surface and therefore it cannot help but complicate the manufacturing process. As a result, the cost of the semiconductor device is raised and the yield thereof is lowered.
As a solution to this, a semiconductor device in which all TFTs have the same polarity has been devised. When all TFTs have the same polarity, some of manufacture steps such as an impurity element doping step can be omitted from the manufacturing process of the TFTs to avoid an increase in cost and lowering of the yield.
An example of a semiconductor device in which every TFT has the same polarity is described with reference to
FIGS. 5A and 5B
.
FIG. 5A
shows a shift register composed of TFTs that have the same polarity. The shift register has plural stages of pulse output circuits
500
for outputting sampling pulses in response to clock signals and start pulses.
FIG. 5B
is a circuit diagram showing one of the pulse output circuits
500
which is composed of n-channel TFTs.
When a logic circuit is composed of TFTs having the same polarity, for example, n-channel TFTs in
FIG. 5B
, a problem arises in that the amplitude of an output signal (SR OUT) is attenuated compared to the amplitude of input signals (in_L, in_R) due to the threshold of an n-channel TFT connected to a high electric potential side power supply. The pulse output circuit (one of the pulse output circuits
500
) shown in
FIG. 5B
solves this problem by boot strap.
This specification deals with digital circuits and therefore input/output electric potentials are expressed as binary values, Hi and Lo. Since meanings of Hi and Lo are reversed in an n-channel TFT and a p-channel TFT, the terms active electric potential and inactive electric potential may be used. The term active electric potential refers to Hi electric potential in a circuit whose transistors are all n-channel transistors or Lo electric potential in a circuit whose transistors are all p-channel transistors. The term inactive electric potential refers to Lo electric potential in a circuit whose transistors are all n-channel transistors or Hi electric potential in a circuit whose transistors are all p-channel transistors.
It is not always necessary for Hi/Lo electric potentials or active electric potential/inactive electric potential to match the power supply electric potential (VDD/VSS) and it only has to match when viewed as a binary value. For instance, an electric potential lower than VDD by a level corresponding to the threshold of an n-channel transistor is also treated as Hi electric potential. An electric potential that can be restored to the level of VDD/VSS by an amplitude compensating circuit or the like is regarded as the Hi/Lo electric potentials or active electric potential/inactive electric potential.
Next, a brief description is given on the operation of the circuit shown in FIG.
5
B. The TFTs that have the same polarity and constitute the circuit here are all n-channel TFTs and the threshold voltage thereof is uniformly VthN. However, this is not to limit the TFTs constituting the circuit to n-channel TFTs. Instead, the TFTs that constitute the circuit may be all p-channel TFTs.
Some parts of the description on the circuit operation mention the operation of the TFTs. Turning a TFT ON means that the absolute value of the gate-source voltage of the TFT becomes higher than the absolute value of the threshold voltage of the TFT and a source region and drain region of the TFT are made to be conductive through its channel formation region. Turning a TFT OFF means that the absolute value of the gate-source voltage of the TFT becomes lower than the absolute value of the threshold voltage of the TFT and a source region and drain region of the TFT are made to be non-conductive.
In describing connection of TFTs, “a gate electrode, an input electrode, an output electrode” and “a gate electrode, a source region, a drain region” are used in different contexts. This is because the gate-source voltage often appears in explaining the operation of a TFT but it is d
Fish & Richardson P.C.
Le Don
Semiconductor Energy Laboratory Co,. Ltd.
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