Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-12-23
2004-12-07
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S365000, C257S390000, C365S185040
Reexamination Certificate
active
06828627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
A well-known semiconductor device is described with reference to
FIGS. 10
to
13
.
This semiconductor device is a NAND cell-type EEPROM as one of electrically-rewritable and -erasable non-volatile semiconductor devices.
FIG. 10
shows an equivalent circuit of the EEPROM.
FIG. 11
illustrates its layout.
FIGS. 12 and 13
are sectional views taken along the lines A-A′ and B-B′, respectively, in FIG.
11
.
The NAND cell-type EEPROM is provided with NAND cell sections
40
11
,
40
12
,
40
21
and
40
22
arranged in a matrix, as shown in FIG.
10
. Each NAND cell section
40
ij
(i=1, 2, j=1, 2) has memory cells MC
1
, MC
2
, . . . , and MC
n
. Each memory cell MC
i
(i=1, . . . ,n) is made up of a stacked transistor having a floating gate
6
and a control gate
8
stacked on a semiconductor substrate
2
via an insulating film
7
, as shown in
FIGS. 10 and 12
. The memory cells MC
1
, . . . , and MC
n
in each NAND cell section are connected in series to share the source and drain between adjacent memory cells.
Each NAND cell section
40
ij
(i=1, 2, j=1, 2) has a drain connected to a bit line BL
j
via a selection transistor SDT
ij
and a source connected to a source line SL
j
via a selection transistor SST
ij
. The source line SL
j
(j=1, 2) is formed by diffused layer interconnection, having a source-line contact
44
thereon, as shown in
FIGS. 11 and 12
.
The sources of the selection transistors STD
1j
and STD
2j
connected to the NAND cell sections
40
1j
and
40
2j
(j=1, 2) aligned in the column direction are connected to the bit line BL
j
via a bit-line contact
42
j
, as shown in
FIGS. 10 and 11
.
The control gate of the memory cell
k
(k=1, . . . ,n) of each of the NAND cell sections
40
11
and
40
12
, and
40
21
and
40
22
aligned in the traverse, respectively, is connected to a word line WL
k
.
The gates of the selection transistors SDT
11
and SDT
12
are connected to a selection line SD
1
, and those of the selection transistors SDT
21
and SDT
22
are connected to a selection line SD
2
, as shown in FIG.
10
.
The gates of the selection transistors SST
11
and SST
12
are connected to a selection line SS
1
, and those of the selection transistors SST
21
and SST
22
are connected to a selection line SS
2
, as shown in FIG.
10
.
The NAND cell section
40
ij
(i=1, 2, j=1, 2), the selection transistors SDT
ij
(i=1, 2, j=1, 2) and SST
ij
(i=1, 2, j=1, 2) and also a silicon nitride film
12
are covered with an interlayer dielectric
22
formed on which are the bit line
i
(i=1, 2), as shown in
FIGS. 12 and 13
.
Each memory cell, selection transistor and also a element isolation region
4
of the well-known EEPROM are covered with the silicon nitride film
12
that will act as a barrier insulating film for contact formation.
This structure offers miniaturization of bit-line and source-line contact regions (diffused layer regions) and protection of the element isolation region
4
including silicon oxide adjacent to the contact regions from dielectric breakdown which would otherwise occur, such that, a contact in the interlayer dielectric
22
, for example, a contact
42
2
punches therethrough and electrically contact with the semiconductor substrate
2
, as illustrated in FIG.
13
.
As illustrated in
FIG. 14
, each memory cell of the well-known EEPROM is formed such that an interface
82
between the silicon nitride film
12
and a silicon oxide film
5
a
on a diffused layer
9
is located under (at the substrate
2
side) an interface
84
between the floating gate
6
and a gate insulating film
5
.
As described, each memory cell of the well-known semiconductor device is covered with a silicon nitride film.
The well-known semiconductor device has, however, drawbacks as discussed below.
First of all, as illustrate in
FIG. 14
, in data-writing/erasing, carriers pass through the gate insulating film
5
and some of them are trapped by the silicon nitride film
12
close to the gate insulating film
5
and also the interface
82
between the silicon nitride film
12
and the silicon oxide film
5
a.
This causes induction of carriers of the opposite polarity on the surface of the diffused layer
9
to increase parasitic resistance to the layer
9
, thus reducing a transistor driving force. Increase in parasitic resistance to the diffused layer of a NAND cell-type EEPROM poses a big problem because it has memory cells series-connected via the layer
9
.
Such parasitic resistance further increases to affect miniaturization of memory cells when decreasing a dose of ions to the diffused layer for reduction of short channel effect.
A numeral
10
in
FIG. 14
represents a silicon oxide film formed by post-oxidation for recovery from damage to the device caused by gate formation.
Another drawback to the well-known semiconductor device is that hydrogen involved in the silicon nitride film
12
degrades the gate insulating film
5
close to the film
12
, thus lowering reliability in transistor performance.
SUMMARY OF THE INVENTION
A purpose of the present invention is to provide a semiconductor device that is protected from reduction in transistor driving force and reliability.
The present invention provides a semiconductor device including: at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode; and a barrier insulating film formed so as to cover the transistor and the diffused layer, wherein a height from a surface of the semiconductor substrate to the barrier insulating film is greater than a height from the surface of the semiconductor substrate, of an interface between the gate insulating film and the gate electrode.
An inter-film may be formed between the diffused layer and the barrier insulating film.
The inter-film may be made of a material different from that of the barrier insulating film.
The semiconductor substrate may be made of silicon and the barrier insulating film may be made of silicon nitride.
The inter-film may include silicon oxide.
The inter-film may be made of a conductive material.
The inter-film may include silicon doped impurities of the same conductive type as that of the diffused layer.
The inter-film may include a silicide.
The inter-film is preferably thicker than the gate insulating film.
The present invention provides a semiconductor device including: at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode; and a barrier insulating film formed so as to cover the transistor and the diffused layer, a distance between a side face of the gate electrode and the barrier insulating film being larger than a thickness of the gate insulating film.
The transistor may make up of a memory cell of an EEPROM.
REFERENCES:
patent: 4931847 (1990-06-01), Corda
patent: 5190888 (1993-03-01), Schwalke
patent: 5237188 (1993-08-01), Iwai
patent: 5324974 (1994-06-01), Liao
patent: 5734607 (1998-03-01), Sung
patent: 5877980 (1999-03-01), Mang
patent: 6703669 (2004-03-01), Goda et al.
patent: 64-5067 (1989-01-01), None
patent: 11-111858 (1999-04-01), None
patent: 2000-58680 (2000-02-01), None
patent: 2000-196046 (2000-07-01), None
Arai Norihisa
Aritome Seiichi
Goda Akira
Hazama Hiroaki
Iizuka Hirohisa
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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