Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-12-27
2004-08-31
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S787000, C257S723000
Reexamination Certificate
active
06784529
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Technical Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to the semiconductor device of a package-stacked structure, having increased memory capacity without increasing a mounting area.
2) Description of Related Arts
As a digital equipment incorporating such a semiconductor device, for example, a semiconductor memory device become more compact and lighter, it has been demanded that the mounting area of the semiconductor device on the mother board is reduced and the memory capacity per unit memory area is increased. One solution for satisfying this demand was, for example, to utilize a semiconductor device having a Small Outline Package (SOP) illustrated in
FIGS. 6 and 7
.
Shown in
FIGS. 6 and 7
are a side and top views, respectively, of the semiconductor device
500
of the package-stacked structure having two semiconductor packages, i.e., SOPs
510
,
520
. The SOPs
510
,
520
have rectangular planar configurations and two pairs of side surfaces opposing to each other. Also, the SOPs
510
,
520
include package bodies
511
,
521
having a plurality of outer lead frames
512
,
522
extending one and other pairs of side surfaces, respectively. The outer lead frames
522
of the SOP
520
are designed such that they are longer than the outer lead frames
512
of the SOP
510
.
According to the semiconductor device
500
shown in
FIG. 7
, the SOP
520
is stacked on the SOP
510
while the outer lead frames
512
,
522
extend to the different directions (with about 90 degrees phase difference) so that the memory capacity per unit mounting area can be increased.
However, in the semiconductor device
500
, the outer lead frames
512
,
522
can extend only to four directions, it is quite difficult to further increase the lead frames so as to realize high-density lead frames.
Further, in case where the semiconductor device has the package-stacked structure of three semiconductor packages, the outer lead frames of the top and bottom SOPs may adversely contact each other. To avoid the disadvantage, the outer lead frames of the top SOP must extend longer in lateral directions, which causes the mounting area of the semiconductor device increased.
SUMMARY OF THE INVENTION
One of the aspects according to the present invention can provide a semiconductor device having package-stacked structure which realizes higher dense lead frames, also provide a semiconductor device having package-stacked structure of three or more semiconductor packages without increasing the mounting area.
A first aspect of the present invention is to provide a semiconductor device including a first semiconductor package having upper and lower surfaces. The first semiconductor package has a plurality of land terminals on the lower surface. The semiconductor device also includes a second semiconductor package having a planar configuration substantially the same as that of the first semiconductor package, which is provided on the upper surface of the first semiconductor package. The second semiconductor package has a plurality of lead terminals extending from a side surface of the second semiconductor package.
A second aspect of the present invention is to provide a semiconductor device including a first semiconductor package having an upper and lower surfaces. The first semiconductor package has a plurality of land terminals on the lower surface. The semiconductor device also includes a second semiconductor package having a planar configuration substantially the same as that of the first semiconductor package, which is provided on the upper surface of the first semiconductor package. The second semiconductor package has a plurality of lead terminals extending from a side surface of the second semiconductor package. Each of the lead terminals extends on and along the lower surface of the first semiconductor package.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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Fukuda Tatsuya
Otani Tomokazu
Clark Jasmine
Renesas Technology Corp.
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