Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-04-11
2004-10-26
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S751000
Reexamination Certificate
active
06809419
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique of semiconductor devices, and particularly to a technique which is applicable effectively to the layout of power lines of semiconductor devices.
A semiconductor device including logic circuits, for example, has a fundamental structure of laying internal circuits in the middle of a semiconductor chip (substrate), laying multiple input/output circuit cells to surround the internal circuits, and laying external terminals for the input/output circuit cells. In this structure, multiple power lines having a shape of planar rings (will be termed “ring power lines” hereinafter) running around the outer edge of the internal circuits are laid between the internal circuits and the external terminals thereby to conduct power voltages to the internal circuits and input/output circuit cells. Power conduction to the ring power lines is from the external terminals for power supply.
The inventors of the present invention have studied a technique, in which the external terminals and ring power lines are formed of a same wiring layer. For the connection of an external terminal for power supply to a ring power line which is located inner than the outmost ring power line, the external power supply terminal cannot be connected directly (as a unitary stuff) to the inner ring power line due to the layout of at least the outmost ring power line between the terminal and the inner line, and therefore the external terminal for power supply needs to be connected to the inner ring power line through another wiring layer via thru-holes.
A power line layout technique is disclosed in Japanese Unexamined Patent Publication No. 2000-311964 for example, in which power pads 12 are formed of a wiring layer separately from the wiring layer of power lines, i.e., equivalent to the ring power lines mentioned above, and these members are connected electrically through electrical contacts.
SUMMARY OF THE INVENTION
The inventors of the present invention have found at the first time the following problem in the technique of connecting the external terminals for power supply to the ring power lines by way of other wiring layer via thru-holes.
Namely, the external terminals for power supply are connected to the ring power lines through lines of other wiring layer (bypass lines) having a different sheet resistance, and a resulting increased voltage drop on the power feed path from the external terminals for power supply to the ring power lines can cause the instability of power supply to the input/output circuit cells and internal circuits. This problem becomes pronounced with the enhancement of function of semiconductor devices and the lowering of their power voltage. One reason is that the load current increases with the enhancement of function of semiconductor device, which results in an increased variation of load current and voltage drop in the semiconductor device. Another reason is that the allowable power voltage fluctuation is narrowed in the trend of lower power voltages of semiconductor devices for the sake of lower power consumption and higher durability of elements.
The study conducted by the inventors of the present invention has revealed at the first time that the above-mentioned problem is particularly pronounced for semiconductor devices having different line structures, specifically, having wiring lines comprised of copper (Cu) as main element and wiring lines comprised of aluminum (Al) as main element.
Precise low-resistance line structures using copper as main element and based on the damascene wiring technique are adopted increasingly in recent years. However, the technique of connection between bonding wires and external terminals of copper is still in the development stage, whereas the connection between bonding wires and external terminals of aluminum is already a common technique and it is inexpensive relative to the use of copper. On this account, even in the copper line structure, an aluminum wiring layer is used for the upmost layer for the sake of connection to the external terminals in many cases. In this case, the difference of sheet resistance between the upmost aluminum wiring layer and the copper wiring layer immediately below it creates a significantly increased voltage drop on the bypass lines from the external terminals for power supply to the ring power lines, causing the instability of power supply.
A conceivable scheme is to increase the width of bypass lines so that their relatively high resistivity is lowered. However, simply widening the wiring lines imposes another problem of a decreased area for the layout of input/output circuit cells.
It is an object of the present invention to provide a technique capable of enhancing the stability of power supply within semiconductor devices.
These and other objects and novel features of the present invention will become apparent from the following description and accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
The present invention resides in a layout structure of power lines in a semiconductor device, in which multiple external terminals are connected directly on a same wiring layer to multiple first power lines which are laid to run around the outer edge of a first circuit area.
The present invention resides in a layout structure of power lines in a semiconductor device, in which wiring lines of the upmost wiring layer which are comprised of aluminum as main element are lower in sheet resistance than wiring lines of the wiring layer immediately below the upmost wiring layer which are comprised of copper as main element.
REFERENCES:
patent: 6150726 (2000-11-01), Feilchenfeld et al.
patent: 6633082 (2003-10-01), Oda et al.
patent: 6674167 (2004-01-01), Ahn et al.
patent: 2000-311964 (2000-11-01), None
Kuwata Makoto
Minami Toshiaki
Sakuta Toshiyuki
Hitachi , Ltd.
Miles & Stockbridge P.C.
Pham Long
Trinh Hoa B.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3299358