Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-07-17
2004-08-10
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S027000, C326S082000
Reexamination Certificate
active
06774674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a level shifting circuit for a power device preventing a malfunction resulting from a dv/dt transient signal.
2. Description of the Background Art
FIG. 36
shows the structure of a level shifting circuit
90
for a conventional power device. The structure shown in
FIG. 36
is disclosed in Japanese Patent Laying-Open Gazette No. 9-200017 (1997).
Referring to
FIG. 36
, power devices
12
and
13
such as IGBTs (insulated gate bipolar transistors) are totem-pole-connected between a positive electrode and a negative electrode (ground potential GND) of a power source PS, to form a half-bridge power device. Freewheel diodes D
1
and D
2
are connected with the power devices
12
and
13
respectively in an antiparallel manner. A load (an inductive load such as a motor)
14
is connected to a node N
1
between the power devices
12
and
13
.
Referring to
FIG. 36
, the power device
12
, switching between a reference potential defined by the potential of the node N
1
between the power devices
12
and
13
and a power supply potential supplied by the power source PS, is referred to as a high-potential side power device.
The power device
13
, switching between a reference potential defined by the ground potential and the potential of the node N
1
, is referred to as a low-potential side power device.
Therefore, the level shifting circuit
90
shown in
FIG. 36
is divided into a high-potential side power device driving circuit HD and a low-potential side power device driving circuit LD.
The high-potential side power device driving circuit HD has NMOS transistors
24
and
25
serially connected between a positive electrode and a negative electrode of a high-potential side power source
10
for the driving circuit HD, and switches the power device
12
by complementarily turning on/off the NMOS transistors
24
and
25
. The negative electrode of the high-potential side power source
10
is connected to the node N
1
. The voltage of the node between the NMOS transistors
24
and
25
is referred to as a high-potential side output voltage HO.
The high-potential side power device driving circuit HD has a pulse generation circuit
3
generating pulsing ON and OFF signals in response to positive level transition and negative level transition of a pulsing input signal S
1
, supplied from an externally provided microcomputer or the like, generated with reference to the ground potential for driving the NMOS transistors
24
and
25
.
Two outputs of the pulse generation circuit
3
are connected to the gate electrodes of high withstand voltage N-channel field-effect transistors (hereinafter referred to as HNMOS transistors)
4
and
5
which are level shifting transistors. The ON and OFF signals are supplied to the gate electrodes of the HNMOS transistors
4
and
5
respectively.
The drain electrodes of the HNMOS transistors
4
and
5
are connected to first ends of resistors
29
and
30
as well as to inputs of inverter circuits
6
and
7
respectively.
Outputs of the inverter circuits
6
and
7
are connected to an input of a protective circuit
8
having an output connected to set and reset inputs of an SR flip-flop circuit
9
. The protective circuit
8
, serving as a filter circuit for preventing the SR flip-flop circuit
9
from a malfunction, is formed by a logic gate. The protective circuit
8
may also be referred to as a filter circuit
8
.
A Q output of the SR flip-flop circuit
9
is connected to the gate electrode of the NMOS transistor
24
as well as to an input of an inverter circuit
23
having an output connected to the gate electrode of the NMOS transistor
25
.
Second ends of the resistors
29
and
30
are connected to the drain electrode of the NMOS transistor
24
, i.e., the positive electrode (the voltage thereof is referred to as a high-potential side floating power supply absolute voltage VB) of the high-potential side power source
10
. The source electrode of the NMOS transistor
24
, i.e., the negative electrode (the voltage thereof is referred to as a high-potential side floating power supply offset voltage VS) of the high-potential side power source
10
is connected to anodes of diodes
21
and
22
having cathodes connected to the drain electrodes of the HNMOS transistors
4
and
5
respectively.
The low-potential side power device driving circuit LD has NMOS transistors
27
and
28
serially connected between a positive electrode (the voltage thereof is referred to as a low potential side fixed power supply voltage VCC) and a negative electrode (ground potential) of a low-potential side power source
11
for the driving circuit LD, and switches the power device
13
by complementarily turning on/off the NMOS transistors
27
and
28
. The voltage of the node between the NMOS transistors
27
and
28
is referred to as a low potential side output voltage LO, whose change defines a control signal S
7
for controlling the power device
13
. The NMOS transistor
27
is controlled by an externally supplied input signal S
0
, while the NMOS transistor
28
is controlled by a signal obtained by inverting the input signal S
0
by an inverter circuit
26
.
Operations of the level shifting circuit
90
are now described with reference to a timing chart shown in FIG.
37
.
Referring to
FIG. 37
, the pulse generation circuit
3
successively generates pulses as ON and OFF signals S
2
and S
3
respectively in response to positive level transition and negative level transition of the externally supplied pulsing input signal S
1
.
First, a pulse signal making transition to a high potential is supplied as the OFF signal S
3
. At this time, the OFF signal S
3
is at a low potential, and the HNMOS transistor
4
is turned on by the ON signal S
2
. The HNMOS transistor
5
is in an OFF state.
Thus, the resistor
29
connected to the HNMOS transistor
4
causes a voltage drop, for inputting a low-level signal in the inverter circuit
6
. On the other hand, the resistor
30
connected to the HNMOS transistor
5
causes no voltage drop, for continuously inputting a high-level signal in the inverter circuit
7
. Thus, the inverter circuit
6
outputs a pulse signal S
4
making transition to a high level, while the inverter
7
outputs a signal S
5
remaining low.
The protective circuit
8
receiving the output signals S
4
and S
5
from the inverter circuits
6
and
7
outputs a pulse signal S
6
and a low-level signal S
7
in correspondence to the output signals S
4
and S
5
from the inverter circuits
6
and
7
respectively.
Also when a pulse signal making transition to a high potential is supplied as the OFF signal S
3
, the level shifting circuit
90
performs operations similar to the above so that the protective circuit
8
outputs a pulse signal S
7
and a low-level signal S
6
in correspondence to the output signals S
5
and S
4
from the inverter circuits
7
and
6
respectively.
Consequently, an output signal S
8
from the SR flip-flop circuit
9
goes high at a timing supplied with the ON signal S
2
and goes low at a timing supplied with the OFF signal S
3
. A similar control signal S
9
for the power device
12
is obtained by complementarily turning on/off the NMOS transistors
24
and
25
.
Depending on the switching state of the half-bridge power device formed by the power devices
12
and
13
, a dv/dt transient signal is disadvantageously generated in a line connecting the node N
1
and the anodes of the diodes
21
and
22
.
When the dv/dt transient signal is generated, a dv/dt current obtained by integrating drain-to-source parasitic electrostatic capacitances of the HNMOS transistors
4
and
5
and the dv/dt transient signal simultaneously flows to the HNMOS transistors
4
and
5
.
Thus, it follows that error pulses P
1
and P
2
resulting from the dv/dt transient signal are simultaneously supplied as the signals S
2
and S
3
in place of the ON and OFF signals, while the protective circuit
8
i
Araki Toru
Okamoto Kazuaki
Mitsubishi Denki & Kabushiki Kaisha
Tran Anh Q.
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